Output buffer circuit utilizing FETS for lowering output resista

Details Output buffer circuit utilizing FETS for lowering output resista Output buffer circuit utilizing FETS for lowering output resista

1996-07-01

1999-02-09

Santamauro, Jon

Electronic digital logic circuitry

Interface

Current driving

326 17, 326 30, H03K 190185, H03K 190948

Patent

active

058699848

ABSTRACT:
An output buffer circuit includes a portion for receiving an input signal in which a level thereof is changed from a high level to a low level and vice versa, and a circuit block for operating based on the input signal received by the portion and for outputting an output signal in which a level thereof is changed from a high level to a low level and vice versa in response to level transition of the input signal, the circuit block including a circuit arrangement of a plurality of FETs for temporarily lowering an output resistance of the circuit block in level transition of the output signal.

REFERENCES:
patent: 4877978 (1989-10-01), Platt
patent: 5066873 (1991-11-01), Chan et al.
patent: 5087840 (1992-02-01), Davies et al.
patent: 5128560 (1992-07-01), Chern et al.
patent: 5153450 (1992-10-01), Ruetz
patent: 5153455 (1992-10-01), Walters, Jr.
patent: 5206544 (1993-04-01), Chen et al.
patent: 5387824 (1995-02-01), Michelsen

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