Output buffer circuit that can be shared by a plurality of inter

Details Output buffer circuit that can be shared by a plurality of inter Output buffer circuit that can be shared by a plurality of inter

1995-04-21

1996-06-25

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 63, 326 49, H03K 19094

Patent

active

055303790

ABSTRACT:
First and second transistors are connected via a first switch. Second and third transistors are connected in parallel via a second switch. Either an input signal or an output ground voltage is applied to the gate of a third transistor via a third switch. In a LVTTL version, the first switch is on and the second switch is off. By the third switch, the output ground voltage is applied to the gate of the third transistor. As a result, first and second, transistors are arranged in series between the output power supply voltage and the output ground voltage, resulting in an output buffer circuit corresponding to a LVTTL. In a GTL version, the first switch is off and the second switch is on. An input signal is applied to the gate of the third transistor by the third switch. As a result, second and third transistors are arranged in parallel to form an open drain. This can be used as an output buffer circuit corresponding to a GTL.

REFERENCES:
patent: 4223277 (1980-09-01), Taylor et al.
patent: 4616147 (1986-10-01), Pumo
patent: 4644187 (1987-02-01), Haji
patent: 5059835 (1991-10-01), Lauffar et al.
patent: 5298807 (1994-03-01), Salmon et al.
patent: 5304872 (1994-04-01), Avraham et al.
patent: 5450027 (1995-09-01), Gabara
"WP3.7: A CMOS Low.varies.Voltage-Swing Transmission-Line Transceiver", Bill Gunning et al., ISSCC 92, Session 3, High-Performance Circuits, pp. 58-59, Feb. 19, 1992.

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