Output buffer circuit, memory chip, and semiconductor device...

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

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Details

C326S030000, C326S085000, C326S087000, C365S189050, C365S189080

Reexamination Certificate

active

06919738

ABSTRACT:
An output buffer circuit including a programmable impedance buffer configured to match a buffer size thereof with an external impedance, a buffer size decision circuit configured to generate a plurality of buffer size signals for determining the buffer size of the programmable impedance buffer synchronized with a first clock signal, and an impedance adjustment circuit configured to adjust the buffer size based on the buffer size signals in response to a level of an output data signal.

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Harold Pilo, et al., “A 300MHz, 3.3V 1Mb SRAM Fabricated in a 0.5μm CMOS Process”, 1996 IEEE International Solid-State Circuits Conference, ISSCC96/Session 9/SRAM/Paper FA 9.3, 1996 Digest of Technical Papers, 42nd ISSCC, pp. 148-149, 433.

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