Output buffer circuit having reduced switching noise

Details Output buffer circuit having reduced switching noise Output buffer circuit having reduced switching noise

1994-09-20

1995-09-05

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 58, 326 83, H03K 1716, H03K 190948

Patent

active

054481813

ABSTRACT:
A CMOS or NMOS output buffer equalizes the number of logic gates in the signal paths connected to both the pull up and pull down transistors. In one embodiment, the pull down transistor signal path includes the conventional inverter connected to the output of a NAND gate. The pull up transistor signal path includes a CMOS passgate including two transistors connected together controlled by the output enable signal and passing the output data signal to a conventional output inverter stage. Also an additional transistor controlled by the output enable signal provides an additional signal to the input of the pull up transistor output inverter stage when the output enable signal is low. The provision of balanced signal paths in terms of number of gates and therefore propagation time to both the pull up and pull down transistors evens out the rise and fall crowbar switching current and thus minimizes switching noise.

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