Output buffer circuit having low breakdown voltage

Electronic digital logic circuitry – Interface – Logic level shifting

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326 57, 326 80, 326 83, 326112, 327543, H03K 19094, H03K 1900, H03K 190175, H03K 1920, G05K 302

Patent

active

060642270

ABSTRACT:
In an output buffer circuit, a logic circuit generates first and second data signals each having a voltage level between a low voltage and a first high voltage. A level shift circuit receives the first data signal and generates a third data signal having a voltage between a first intermediate voltage and a second high voltage higher than the first high voltage. An output circuit includes first and second P-channel MOS transistors and first and second N-channel MOS transistors powered by the low voltage and the second high voltage, a gate of the first P-channel MOS transistor receives the third data signal, a gate of the second P-channel MOS transistor receives a second intermediate voltage between the low voltage and the second high voltage, a gate of the first N-channel MOS transistor receives the data signal, and a gate of the second N-channel MOS transistor receives a third intermediate voltage.

REFERENCES:
patent: 5539334 (1996-07-01), Clapp, III et al.
patent: 5565811 (1996-10-01), Park et al.
patent: 5684415 (1997-11-01), McManus
patent: 5729155 (1998-03-01), Kobatake
patent: 5798637 (1998-08-01), Kim et al.

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