Output buffer circuit having a minimized output voltage propagat

Details Output buffer circuit having a minimized output voltage propagat Output buffer circuit having a minimized output voltage propagat

1995-09-29

1997-05-27

Westin, Edward P.

Electronic digital logic circuitry

Accelerating switching

326 27, 326 83, H03K 19017

Patent

active

056336004

ABSTRACT:
In an output buffer circuit so configured that a capacitor connected to a gate of an output driving MOS transistor and including a gate capacitance of the output driving MOS transistor is gradually charged through a resistor, so as to realize a slow rising or falling time, there is additionally provided a threshold voltage charging circuit for rapidly charging the capacitor to a threshold voltage level of the output driving MOS transistor when the output driving MOS transistor is to be turned on. With this arrangement, the propagation delay time of an output voltage can be minimized.

REFERENCES:
patent: 4567378 (1986-01-01), Raver
patent: 5017807 (1991-05-01), Kriz et al.
patent: 5204558 (1993-04-01), Kumaki et al.
patent: 5334889 (1994-08-01), Hisaka
patent: 5471150 (1995-11-01), Jung et al.

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