Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-06-03
2001-09-18
Nguyen, Viet Q. (Department: 2818)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S021000, C326S026000, C326S034000, C326S056000, C326S083000, C327S317000, C327S108000, C327S318000, C327S379000, C327S374000, C327S520000
Reexamination Certificate
active
06292014
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an output buffer circuit for transmitting digital signals over a transmission line with preemphase.
DESCRIPTION OF RELATED ART
Digital communication systems have experienced an enormous growth in complexity and operating speed. This results in increasing demands on those system components which serve to interface different system sections with each other. Within a digital system, transmission lines are an appropriate means for interconnecting system sections with each other. Depending on the operating speed, traces on a printed circuit board with the length of a few centimeters must be treated as a transmission line in order to avoid distortion of the transmitted digital signals due to mismatch conditions of the output buffer circuit driving the transmission line and the input buffer circuit receiving the transmitted signals at the other end of the line. Distortions of the transmitted signal due to reflections can be reduced and the data transmission speed can be increased if also the source impedance of the output buffer circuit matches the characteristic impedance of the transmission line.
It is a well known problem with bandwidth limited media, e.g. real transmission lines like cable, printed circuit board traces etc., that when increasing the transmission speed or the length of the transmission media, the signal at the receiver end will deteriorate even if no mismatch condition is present. Such deterioration results from the fact that higher frequency components of the signal suffer from a higher loss in the media than signal components with lower frequencies. This non-uniform loss characteristic of the transmission media distorts the shape of transmitted digital signals at the receiver end of the media. For instance, a single digital zero or one will not reach its full signal amplitude at the receiver's end, which might lead to errors in the detection of the logical level of the signal. This distortion of the signal symbols used for transmitting logical levels, can also be called data dependent distortion or intersymbol interference.
There exist well known methods of compensating the adverse effects of the transmission media on the transmitted signal. One of such methods is, to apply a preemphase distortion to the signal in the output buffer driving the line. The pre-emphase distortion of the transmitted signal takes into account the frequency dependent losses of the signal in the transmission media such that at the receiver end the adverse effect of intersymbol interference can be alleviated or compensated. A well known, simple way to provide a pre-emphase distortion is, to increase the signal amplitude of a single digital zero or a single digital one in order to compensate the distortion of the single symbols at the receiver end. An output buffer circuit with the ability to provide a pre-emphase on the output signal, determines the output amplitude dependent on the present logical level of the data input signal to be transmitted, and the history of the data input signal, e.g. the logical level of the data input signal one bit clock period ago.
From U.S. Pat. No. 5,243,229 an output buffer circuit is known, that delivers a digital signal to a transmission line. The known circuit is able to generate a binary signal with a digitally adjustable source impedance. The known circuit consists of a series connection of two digital impedances. In accordance with a data input signal, one of these digital impedances is active while the other digital impedance is inactive, i.e. in a high impedance state. Both digital impedances are controlled such that their impedance values in the active state are equal. Each digital impedance consists of a parallel connection of MOSFET transistors. A control circuit is provided which activates as many of the MOSFETs as necessary for achieving the target impedance in the active state. However, outputting a signal with pre-emphase requires, that the output buffer circuit is able to generate more than two distinct output signal levels. The circuit known from this document is not able to meet this objective.
SUMMARY OF THE INVENTION
It is the object of the present invention, to provide an output buffer circuit for driving a transmission line that is able to generate an output signal for transmission with a pre-emphase distortion and with a constant output impedance.
According to the present invention, this object is solved as defined in the independent patent claims. Advantageous embodiments of the present invention are given in the dependent claims.
An output buffer circuit according to an embodiment of the present invention comprises an output stage that includes a first impedance circuit and a second impedance circuit. The first impedance circuit is connected to provide a first impedance between an upper power supply node and an output terminal for connection with the transmission line, the first impedance being controllable in accordance with a first impedance control signal. The second impedance circuit is connected to provide a second impedance between a lower power supply node and said output terminal. The second impedance is controllable in accordance with a second impedance control signal. A control circuit is provided for receiving a digital data input signal and for generating the impedance control signals for the first impedance circuit and the second impedance circuit, in accordance with said digital data input signal. The control circuit generates the impedance control signals for the first impedance circuit and the second impedance circuit such that the ratio of the first impedance and the second impedance can take one of at least three different predetermined values, in accordance with the present state and the history of the digital data input signal, in order to generate an output signal for the transmission line with a pre-emphase distortion. Moreover, the control circuit generates the impedance control signals for the first impedance circuit and for the second impedance circuit such that the sum of the conductance provided by the first impedance circuit and the conductance provided by the second impedance circuit, is independent from the generated impedance ratios.
If the sum of the conductances of the first impedance circuit and the second impedance circuit, i.e. the sum of the inverse of the first impedance and the inverse of the second impedance, is the same for all impedance ratios generated under control of the control circuit, the output impedance of the output buffer circuit will be substantially constant for all generated signal levels occurring in the output signal with pre-emphase.
Preferably, each impedance circuit comprises a plurality of transistors having their drain source paths connected in parallel. The transistors receive at their gates individual control signals for turning the respective transistor OFF or ON. The ON resistance of the transistor is determined by physical design parameters of the transistor, e.g. the channel width and the channel length of the transistor.
Preferably, the parallel connected transistors of each impedance element are designed such that their respective ON impedances are in a binary relation with each other, i.e. the ON impedance of the n-th transistor of each impedance element is equal to 2
n−1
times the ON impedance of transistor
1
of that impedance circuit. This can e.g. be achieved by means of designing the transistors of each impedance circuit such that W(n)=2
−(n−1)
·W(1), W(n) being the channel width of transistor element n of the impedance circuit.
Preferably, the impedance circuits of the output stage comprise similar sets of transistors. Transistors corresponding to each other in the first impedance circuit and in the second impedance circuit which have the same properties, are preferably driven such that the transistor in one impedance circuit is switched OFF when the corresponding transistor in the other impedance circuit is switched ON, e.g. by means of driving the gates of
Jenkens & Gilchrist a Professional Corporation
Nguyen Viet Q.
Telefonaktiebolaget LM Ericsson
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