Output buffer circuit for memory device

Details Output buffer circuit for memory device Output buffer circuit for memory device

1994-12-22

1996-07-16

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 58, 326 27, H03K 1716

Patent

active

055370608

ABSTRACT:
An output buffer circuit for a memory device comprising a pull-up path including first and second PMOS transistors for forming two parallel charging paths, and a pull-down path including first and second NMOS transistors for forming two parallel discharging paths. The first and second PMOS transistors are selectively operated according to a level of an output voltage at an output terminal to perform a charging operation for a load capacitance connected to the output terminal. The first and second NMOS transistors are selectively operated according to the level of the output voltage at the output terminal to perform a discharging operation for the load capacitance through a lead inductance.

REFERENCES:
patent: 4959561 (1990-09-01), McDermott
patent: 5057711 (1991-10-01), Lee
patent: 5319260 (1994-06-01), Wanless
patent: 5332932 (1994-07-01), Runaldue
patent: 5426376 (1995-06-01), Wong

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