Output buffer circuit for interfacing semiconductor integrated c

Details Output buffer circuit for interfacing semiconductor integrated c Output buffer circuit for interfacing semiconductor integrated c

1995-10-25

1997-05-20

Westin, Edward P.

Electronic digital logic circuitry

Tri-state

With field-effect transistor

326 81, 326 83, H03K 190185

Patent

active

056315791

ABSTRACT:
An output buffer circuit operating normally when its supply potential is exceeded by the potential of the bus to which the buffer circuit output is connected. The circuit comprises a p-channel MOS transistor and a first and a second n-channel MOS transistor. The output node of the output buffer circuit is connected not to the p-channel MOS transistor but to the connection point between the source of the first n-channel MOS transistor and the drain of the second n-channel MOS transistor. The threshold potential of the first n-channel MOS transistor is set so that, with the output node in the high-impedance state, the first n-channel MOS transistor is turned off when the output node potential exceeds the supply potential of the output buffer circuit. This prevents the p-channel MOS transistor from getting activated or from being forward-biased between the back gate and the drain or source. Thus no leak current flows when the bus potential becomes higher than the supply potential of the output buffer circuit.

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