Output buffer circuit for excessive voltage protection

Details Output buffer circuit for excessive voltage protection Output buffer circuit for excessive voltage protection

2002-12-03

2004-07-13

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S027000, C327S108000

Reexamination Certificate

active

06762622

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an output buffer circuit, especially to an output buffer circuit for excessive voltage protection, whereby the risk of device damage and the leak current can be prevented.
BACKGROUND OF THE INVENTION
The developing trends of microelectronic device are more compact size and higher integration on a single chip. As the demand of higher integration and operation speed, the microelectronic device is forced to use lower operation voltage than commonly used rate voltage for reducing power consumption. Therefore, a buffer circuit should be provided between an external circuit and the microelectronic device to adapt a signal voltage difference and to protect a chip core circuit in the microelectronic device.
FIG. 1
shows a conventional output buffer circuit, which is connected between a data out
161
of the chip core and an I/O pad
145
in the demonstrated example. The data out
161
is connected to a first input end of an AND gate
141
and an output control
163
is connected to a second input end of the AND gate
141
. The output end of the AND gate
141
is commonly connected to a pull-up circuit and a pull-down circuit at a node
181
. The signal of the data out
161
of the chip core is transmitted to the I/O pad
145
through either the pull-up circuit or the pull-down circuit. The pull-up circuit comprises a pull-up transistor
121
and a protective transistor
123
. The pull-up transistor
121
has a drain connected to an external voltage source VPP, a source connected to a drain of the protective transistor
123
, and a gate connected to the node
181
. The protective transistor
123
has a source connected to the I/O pad
145
through a node
183
, a gate connected to the external voltage source VPP to form a protective element. The pull-up transistor
121
is turned on or off by the data out
161
and the voltage level at the node
183
is conditionally boosted by the pull-up transistor
121
.
The pull-down circuit has an inverter
143
, a pull-down transistor
127
and a protective transistor
125
. The protective transistor
125
has a drain connected to the node
183
, a source connected to a drain of the pull-down transistor
127
, and a gate connected to the external voltage source VPP to form a protective element. The pull-down transistor
127
has a source connected to a ground voltage VGG. The inverter
143
has an input end connected to the node
181
and an output connected to a gate of the pull-down transistor
127
. When the data out
161
is a low output (“zero”), the voltage at the node
181
is also a low output. At this time, the inverter
143
has a high output to turn on the pull-down transistor
127
and the voltage level at the node
183
is dropped to provide a low-level output for the I/O pad
145
.
The above-mentioned output buffer circuit provides voltage buffer for the chip core circuit and external circuit. However, the above-mentioned output buffer circuit uses two cascaded transistors, which occupies considerable area due to increased channel width. The channel width should be increased to provide compatible current driving ability as single transistor in condition of same channel length.
Moreover, the output buffer circuit in scheme of two cascaded transistors also hinders a discharge path between the I/O pad
145
and VPP/VGG for electrostatic discharge (ESD). It is difficult to turn on transistors in cascaded arrangement.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an output buffer circuit for excessive voltage protection, whereby the risk of device damage and the leak current can be prevented.
In one aspect of the present invention, the output buffer circuit for excessive voltage protection uses a stage of pull-up transistor as output buffer with reduced occupied area.
In another aspect of the present invention, the output buffer circuit for excessive voltage protection uses s a stage of pull-up transistor with a boost circuit on a gate thereof. The gate voltage of the pull-up transistor is sustained to a certain high level when the pull-up transistor is turned off. The voltage difference between the gate voltage and the source voltage of the pull-up transistor can be reduced. The risk of device damage and the leak current can be prevented.
In still another aspect of the present invention, the output buffer circuit for excessive voltage protection has a transmission gate for a data out to protect the chip core circuit in the microelectronic device.
In still another aspect of the present invention, the output buffer circuit for excessive voltage protection has a boost circuit with a boost element and a boost-controlling circuit. The boost-controlling circuit senses the excessive voltage at the I/O node and activates the boost element to boost the gate voltage of the pull-up transistor.
In still another aspect of the present invention, the output buffer circuit for excessive voltage protection has an electrostatic discharge (ESD) protecting circuit to provide further protection.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:


REFERENCES:
patent: 5315187 (1994-05-01), Cheng
patent: 5448181 (1995-09-01), Chiang
patent: 5455732 (1995-10-01), Davis

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