Output buffer circuit and system including the output buffer...

Details Output buffer circuit and system including the output buffer... Output buffer circuit and system including the output buffer...

2007-03-27

2008-09-02

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S068000, C326S087000, C327S111000

Reexamination Certificate

active

07420395

ABSTRACT:
An output buffer circuit, which minimizes or prevents output delay of output signal and degradation of slew rate while suppressing overshoot and undershoot, is provided. In a first time period when an input signal to a gate of an N-channel output transistor changes from ‘L’ level to ‘H’ level, the gate is connected to an output terminal through a capacitor element so that the overshoot is suppressed. In addition, the output buffer circuit stores negligible electrical charge in the capacitor element prior to the first time period, which results in minimal delay in outputting a buffered signal and degradation of slew rate while suppressing undershoot when the input signal changes from ‘H’ level to ‘L’ level in the first time period.

REFERENCES:
patent: 5949259 (1999-09-01), Garcia
patent: 6236239 (2001-05-01), Kogushi

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