Electronic digital logic circuitry – Accelerating switching
Patent
1996-05-17
1999-04-27
Santamauro, Jon
Electronic digital logic circuitry
Accelerating switching
326 27, 326 86, H03K 190185
Patent
active
058983155
ABSTRACT:
The present invention concerns a circuit and method for improving the data access times across boundary reads between cascaded buffers, such as FIFOs, that are connected to a common data output bus. The circuit allows read accesses within a cascaded buffer system to have similar access speeds, i.e., a boundary read is not noticeably slower or faster than any other non-boundary read access from an individual buffer in the system. The circuit may not adversely affect the data sheet or operating system parameters, and imposes minimal chip real estate constraints.
REFERENCES:
patent: 4636983 (1987-01-01), Young et al.
patent: 4885485 (1989-12-01), Leake et al.
patent: 5013940 (1991-05-01), Ansel
patent: 5036222 (1991-07-01), Davis
patent: 5329175 (1994-07-01), Peterson
patent: 5450019 (1995-09-01), McClure et al.
patent: 5455521 (1995-10-01), Dobbelaere
patent: 5534806 (1996-07-01), Gowni et al.
patent: 5537060 (1996-07-01), Baek
patent: 5559465 (1996-09-01), Shah
patent: 5600261 (1997-02-01), White et al.
patent: 5623216 (1997-04-01), Penza et al.
patent: 5623221 (1997-04-01), Miyake
patent: 5633600 (1997-05-01), Ohnishi
Arcole; U.S.S.N. 08/777488 Memory Having Selectable Output Strengths; filed Dec. 30, 1996.
Cypress Semiconductor Corp.
Maiorana Christopher P.
Santamauro Jon
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