Output buffer circuit

Details Output buffer circuit Output buffer circuit

2006-08-08

2008-03-25

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S027000, C326S030000

Reexamination Certificate

active

07348794

ABSTRACT:
Disclosed is an output buffer including a first output buffer for data for receiving a data signal and outputting an output signal from an output terminal, a second output buffer with an output end thereof connected to the output terminal, and a selection circuit. The selection circuit receives a control signal indicating whether de-emphasis enabled or de-emphasis is disabled and performs switching control so that when the control signal indicates that the de-emphasis is disabled, the second output buffer is deactivated, when the control signal indicates that the de-emphasis is enabled, emphasis data obtained on delaying the data signal through a delay circuit is supplied to an input end of the second output buffer, thereby causing the second output buffer to operate as a de-emphasis buffer, and when a test control signal is of a value indicating an amplitude margin test, the data signal is selected to be supplied to the input end of the second output buffer.

REFERENCES:
patent: 6674313 (2004-01-01), Kurisu et al.
patent: 6772250 (2004-08-01), Dreps et al.
patent: 6897685 (2005-05-01), Sato
patent: 2006/0006901 (2006-01-01), Groen et al.
patent: 2002-94365 (2002-03-01), None
patent: 2004-88693 (2004-03-01), None

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