Output buffer circuit

Details Output buffer circuit Output buffer circuit

2006-06-27

2006-06-27

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S026000, C326S083000

Reexamination Certificate

active

07068063

ABSTRACT:
An output buffer circuit includes first and second inverters connected to an input terminal for outputting signals having a slow rise up and fall down characteristic; a pull up control circuit that pulls up an output voltage of the first inverter and stops the pull up operation based on a level of the output signal of the first inverter; and a pull down control circuit that pulls down an output voltage of the second inverter and stops the pull down operation based on a level of the output signal of the second inverter. A first output transistor has a source connected to a first power source, a drain connected to the output terminal and a gate connected to the first inverter. A second output transistor has a source connected to a second power source, a drain connected to the output terminal and a gate connected to the second inverter.

REFERENCES:
patent: 4612466 (1986-09-01), Stewart
patent: 5013940 (1991-05-01), Ansel
patent: 5430387 (1995-07-01), Bechade et al.
patent: 5623221 (1997-04-01), Miyake
patent: 5654648 (1997-08-01), Medhekar et al.
patent: 5804990 (1998-09-01), Popat et al.

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