Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-05-10
2001-03-13
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000
Reexamination Certificate
active
06201405
ABSTRACT:
The present invention relates to an output buffer circuit for driving a transmission line in accordance with data to be transmitted, the output buffer circuit being able to adjust the output impedance to match the characteristic impedance of the transmission line.
With the ever increasing operating speed of digital circuitry, also the demands on interfaces linking different circuit components regarding data transmission capacity will increase. The higher the bit rate to be transmitted via a transmission line, the more important is that both the transmitting side and the receiving side connected via a transmission line, have a source impedance and an input impedance, respectively, which match the characteristic impedance of the transmission line. Such impedance matching is inevitable for avoiding reflections on the transmission line which might otherwise disturb data transmission at high data rates.
U.S. Pat. No. 5,134,311 discloses a self-adjusting impedance matching driver circuit having an array of pull-up gates to VDD and an array of pull-down gates to ground. One or more of such gates is selectively enabled in response to circuit means that monitors the impedance match between the output of the driver circuit and the network it drives. For this purpose a comparator has an input connected to the output of the driver circuit and an output that controls latches for selectively enabling one or more of said pull-up gates and other latches for controlling one or more of said pull-down gates, such that closed loop output impedance control is performed.
IEEE International Solid State Circuits Conference 1993, Session 10, High Speed Communication and Interfaces, paper 10.7 discloses a circuit for performing automatic impedance matching between a CMOS output buffer circuit and an externally connected transmission line. According to that proposal, impulses are output by the driver circuit to the transmission line, and during a period of time prior to the arrival of possible reflections from the end of the transmission line, the output voltage of the buffer is controlled to half the supply voltage, implying that then the output impedance of the buffer equals the characteristic impedance of the line. Such control is performed independently for the pull-up gate of the CMOS driver and the pull-down gate of the CMOS driver, each of these gates comprising an array of drive transistors selectively enabled by an impedance control register.
Both these approaches of the prior art adopt some kind of control loop for adjusting the output impedance of a line driver circuit, the control loop including the detection of the actual output impedance and the adjustment of impedance means determining the actual output impedance of the driver, such that the detected output impedance matches a desired value.
However, according to these approaches it is not easily possible to detect the actual output impedance of the output buffer on a continuous basis when the buffer is transmitting data. For this reason the first mentioned approach of setting up the output buffer takes place at power up and thereafter only if the driven network is changed substantially. The second approach suffers from extreme timing demands due to the fact that output impedance detection has to take place before a possible reflection from the end of the transmission line has arrived at its beginning.
It is the object of the present invention, to provide an output buffer circuit having an output impedance self-adjustable to a desired impedance value even during the transmission of data.
According to the present invention, this object is solved as defined in claim
1
. Advantageous embodiments are described in the dependent claims.
An output buffer circuit according to the present invention is able to perform a self adjustment of its output impedance by means of monitoring the output of an output stage to the transmission line. Monitoring is achieved by means of a selector circuit that selectively connects the output port of the output stage to a detection input of an output impedance control circuit in such a manner that the data signal changes at the output port do not adversely affect the detection of the actual output impedance. The timing of this selective connection depends on the data signal output by the output buffer.
In a simple and preferable embodiment the selector circuit operates as a rectifier synchronized with the data signal, for synchronously rectifying the output signal of the buffer circuit. It can comprise a bridge circuit controlled by the data input signal. According to another preferred embodiment the selector circuit is adapted to sample the output signal of the buffer in synchronism with the data signal to be transmitted. Means for holding the sampled signal may be provided if sampling takes place during a fraction of each bit period of the data signal only.
The detection signal output by the selector circuit and indicating the actual source impedance of the output buffer, is used by the impedance control circuit to adjust the output impedance of the buffer circuit in accordance with a reference value. In a simple and preferred embodiment the impedance control circuit comprises control amplifier means connected to receive at its differential inputs, the impedance detection signal and a reference signal, respectively. The output of the control amplifier adjusts or controls the output impedance of the buffer, thus constituting a control loop.
According to a preferred embodiment, the output buffer circuit comprises a series connection of output impedance means for adjusting the output impedance of the buffer, and a switch stage for connection with a transmission line. The switch stage is controlled in accordance with data to be transmitted. The output buffer circuit is designed such that an impedance connected to the output of the switch stage, e.g. a transmission line with termination, constitutes a voltage divider circuit with the output impedance means and with the switch stage connected there between.
If the switch elements included in the switch stage contribute to the overall output impedance, the provision of the selector circuit allows detecting an output voltage of this voltage divider across the output terminals of the buffer circuit substantially unaffected by the switching operation of the switch stage. On the basis of the known impedance connected to the output of the switch stage, the detected voltage indicates the overall impedance of the output buffer including the impedance of the adjustable output impedance means and the impedance of the switch stage. The control circuit can then preferably operate to achieve that the detected voltage across the output of the switch stage equals half the supply voltage of the series connection of output impedance means, switch stage and connected load impedance.
If a plurality of output buffer circuits for a plurality of data channels is provided on the same chip, i.e. on the same semiconductor substrate, use can be made of the fact that each of the individual buffer circuits of the chip can be made to have very similar electrical properties by means of manufacturing all circuits with the same process, as is well known as such. Then the provision of a single selector circuit and a single impedance control circuit may be sufficient for a plurality of buffer circuits each having a switch stage and an output impedance means each receiving the same impedance control signal.
The present invention is advantageous in that it uses the impedance connected to the output buffer, as a reference impedance. The output buffer can, therefor, automatically adapt its output impedance to different load impedances without the need of connecting or adjusting additional external reference impedances, this leading to pin count savings in LSI designs where the number of output pins more and more becomes a critical parameter.
REFERENCES:
patent: 5296756 (1994-03-01), Patel et al.
patent: 5559441 (1996-09-01), Desroches
patent: 5808478 (1998-09-01), Andresen
patent: 5811984 (1998-09-01),
Le Thong
Nelms David
Nixon & Vanderhye
Telefonaktiebolaget LM Ericsson
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