Output buffer circuit

Details Output buffer circuit Output buffer circuit

1986-07-08

1988-09-27

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365189, 365149, 365203, 307530, G11C 1300

Patent

active

047746904

ABSTRACT:
In an output buffer circuit for a memory including complementarily-connected P-channel and N-channel MOS transistors, a voltage is induced across the lead inductance whenever the load capacitance is charged or discharged through the lead inductance during the switching operation of the buffer circuit. This induced voltage changes the ground level or the supply voltage level, and results in a problem such that data signals read from the memory are distorted. To overcome this problem, one of the two MOS transistors through which an electric charge is charged or discharged is divided into two MOS transistors of a small size, and the data signal is applied to one of the divided MOS transistor directly and to the other thereof through a delay element so that the peak of the induced voltage is lowered without increasing the access time of the memory.

Affiliated with

Also associated with

Rating

Output buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Output buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output buffer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2401208