Output buffer apparatus capable of adjusting output...

Details Output buffer apparatus capable of adjusting output... Output buffer apparatus capable of adjusting output...

2005-12-27

2005-12-27

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S032000, C326S034000, C326S087000

Reexamination Certificate

active

06980019

ABSTRACT:
In an output buffer apparatus including a main-buffer circuit including a plurality of first transistors each connected between a first power supply terminal and an output terminal and a plurality of second transistors each connected between a second power supply terminal and the output terminal, and a pre-buffer circuit including a plurality of first pre-drivers each driving one of the first transistors in accordance with a data signal and a plurality of second pre-drivers each driving one of the second transistors in accordance with the data signal, a plurality of first sequential circuits are provided for receiving first impedance adjusting signals in synchronization with the data signal to turn ON the first pre-drivers, and a plurality of second sequential circuits are provided for receiving second impedance adjusting signals in synchronization with the data signal to turn ON the second pre-drivers.

REFERENCES:
patent: 5134311 (1992-07-01), Biber et al.
patent: 5751161 (1998-05-01), Wei et al.
patent: 6094069 (2000-07-01), Magane et al.
patent: 6166563 (2000-12-01), Volk et al.
patent: 6292014 (2001-09-01), Hedberg
patent: 2003/0146774 (2003-08-01), Coughlin et al.
patent: 2002-94366 (2002-03-01), None
Taiwanese Office Action dated Feb. 4, 2005, with English translation.
European Search Report dated Mar. 15, 2004.

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