Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2002-08-06
2004-11-30
Sircus, Brian (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
06826026
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to the field of electrostatic discharge (ESD) protection for output buffers in deep submicron CMOS technologies.
DESCRIPTION OF THE RELATED ART
Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events. A major source of ESD exposure to ICs is from the charged human body (“Human Body Model”, HBM); the discharge of the human body generates peak currents of several amperes to the IC for about 100 ns. A second source of ESD is from metallic objects (“machine nodel”, MM); it can generate transients with significantly higher rise times than the HBM ESD source. A third source is described by the “charged device mode” (CDM), in which the IC itself becomes charged and discharges to ground in the opposite direction than the HBM and MM ESD sources. More detail on ESD phenomena and approaches for protection in ICs can be found in A. Amerasekera and C. Duvvury, “ESD in Silicon Integrated Circuits” (John Wiley & Sons LTD. London 1995), and C. Duvvury, “ESD: Design for IC Chip Quality and Reliability” (Int. Symp. Quality in El. Designs, 2000, pp. 251-259; references of recent literature).
ESD phenomena in ICs are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fields—all factors that contribute to an increased sensitivity to damaging ESD events.
The most common protection schemes used in metal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with an nMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the nMOS device width from the drain to the source under the gate oxide of the nMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that nMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism, found in the nMOS protection device operating as a parasitic bipolar transistor in snapback conditions, is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self-heating. The peak nMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
With the continued scaling in deep submicron technologies, pMOS transistors are now emerging increasingly with their own failure phenomena. In particular, pMOS transistors are starting to show ESD breakdown behavior resulting in sneak current paths. For example, some products failed at 2.5 to 3.0 kV (and could get worse) and the failure was traced to the small pull-up pMOS in the 2 mA buffers. Thorough analysis indicated that the pMOS transistor triggers unexpectedly and cannot handle the current.
Most of the traditional protection schemes consider the current paths from signal pad to Vss or signal pad to Vdd, but do not consider sneak current paths from Vdd back to the signal pad. This sneak current could happen when an I/O pin is stressed negative to Vdd, or, inversely, a positive stress on Vdd appears with respect to I/O.
An urgent need has, therefore, arisen for a coherent, low-cost method of enhancing ESD insensitivity in pMOS devices without the need for additional, real-estate consuming protection devices. The device structures should further provide excellent electrical performance, mechanical stability and high reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
As a first embodiment of the present invention, an output circuit is described for improved ESD protection, comprising a pMOS pull-up output transistor connected between a signal (I/O) pad and Vdd power supply, the pull-up transistor located in a n-well and having at least one gate, the gate connected to internal circuitry; a dummy pMOS transistor connected in parallel with the pull-up transistor, the dummy transistor also located in the n-well, whereby both the pull-up transistor and the dummy transistor participate in protection against an ESD event; the dummy transistor having at least one gate, this gate connected through a resistor to the Vdd power supply; and the n-well connected to the Vdd power supply.
Two more embodiments of the invention are described, which are modifications of the first embodiment. One of these embodiments involves a cascode arrangement of the active and the dummy transistor. As the fourth embodiment of the present invention, a device is discussed providing protection against ESD damage of an integrated circuit signal (I/O) pad; the device comprises a pMOS transistor located in an n-well, the transistor having a plurality of gates. The transistor is connected between the I/O pad and Vdd power supply; the plurality of gates are connected through a resistor to the Vdd power supply; and the n-well is connected to internal circuitry, whereby the device is operable as a lateral pnp transistor for ESD stress between the pad and Vdd, applicable for fail-safe operation, where the I/O pad can reach a higher potential than Vdd.
As the fifth embodiment of the present invention, a device is described providing protection against ESD damage of an integrated circuit signal (I/O) pad, comprising a pMOS transistor located in an n-well, the transistor having a plurality of gates. The transistor is connected between the I/O pad and Vss ground potential; the plurality of gates is connected through a resistor to the I/O pad; and the n-well is connected to the I/O pad, whereby the device is operable as a lateral pnp transistor for positive ESD stress to ground potential, and as a substrate diode for negative ESD stress.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
REFERENCES:
patent: 4775809 (1988-10-01), Watanabe
patent: 5510728 (1996-04-01), Huang
patent: 6444511 (2002-09-01), Wu et al.
Cline Roger A.
Duvvury Charvaka
Brady III W. James
Demakis James A
Sircus Brian
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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