Output buffer

Details Output buffer Output buffer

2006-12-13

2008-12-09

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S027000, C326S030000, C326S087000

Reexamination Certificate

active

07463051

ABSTRACT:
An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transistors have a common conduction terminal connected to an output terminal of the output buffer. An input terminal of the buffer is connected to control terminals of the transistors of the first stage through a first open loop driving circuit. A second feedback driving circuit is connected between the input terminal and the control terminals of the transistors of the second stage. The second feedback driving circuit includes a current detector operating to detect a maximum in the value of the current drawn by and supplied to the output buffer. A comparison block, having a threshold value, detects current in excess of the threshold value and processes information coming from the current detector to regulate an output impedance value of the output buffer. The current detector includes a duplicated structure which replicates a portion of the buffer circuit without altering the performances of the buffer itself.

REFERENCES:
patent: 5313165 (1994-05-01), Brokaw
patent: 6930528 (2005-08-01), Ajit
patent: 7230406 (2007-06-01), Huang et al.
patent: 2003/0071648 (2003-04-01), Heijna et al.
patent: 2004/0090240 (2004-05-01), Ajit
patent: WO 2005/074127 A (2005-08-01), None
Yang, et al., “Output buffer design for low noise and load adaptability,” IEE Proceedings: Circuits Devices and Systems, Institution of Electrical Engineers, Stenvenage, GB, vol. 152, No. 2, Apr. 8, 2005, pp. 146-150, XP006023888; ISSN: 1350-2409.
Ahmad B. Dowlatabadi, “A Robust, Load-Insensitive Pad Driver,” IEEE Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ, US, vol. 35, No. 4, Apr. 2000; XP011061216; ISSN: 0018-92020.
Choy, et al., “A Low Power-Noise Output Driver with an Adaptive Characteristic Applicable to a Wide Range of Loading Conditions,” IEEE Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ, US, vol. 32, No. 6, Jun. 1997; XP011060485, ISSN: 0018-9200.
Bartolini, et al., “A Reduced Output Ringing CMOS Buffer,” IEEE Identification paper No. 2521, Jan. 4, 2006.
Partial European Search Report, EP 05 52 5900, dated Jul. 10, 2006.
Complete European Search Report, EP 05 42 5900, dated Sep. 20, 2006.
A Reduced Output Ringing CMOS Buffer, Bartolini, et al., Circuits and Systems II: Express Briefs, IEEE Transactions on vol. 54, Issue 2, pp. 102-106, dated Feb. 2007.

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