Output buffer

Details Output buffer Output buffer

1995-05-25

1996-11-19

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 87, H03K 190175, H03K 19094

Patent

active

055766412

ABSTRACT:
An output buffer generates "1" or "0" data based on control signals VA and VB transferred from memory cells through a DQ gate in a DRAM. The output buffer has first and second discharge circuits, and a first output transistor (PMOS Transistor). The second discharge circuit stops discharging the gate of the first output transistor after the voltage on the gate drops below the threshold voltage of the first output transistor and the first output transistor turns ON. After this time, only the first discharge circuit discharges the gate of the first output transistor. Further, the output buffer has first and second precharge circuits, and a second output transistor (NMOS transistor). The second precharge circuit stops charging the gate of the second output transistor after the voltage on the gate increases above the threshold voltage of the second output transistor and the second output transistor turns ON. After this time, only the second discharge circuit continues charging the gate of the second output transistor.

REFERENCES:
patent: 4882507 (1989-11-01), Tatsumi et al.
patent: 4908528 (1990-03-01), Huang
patent: 5034629 (1991-07-01), Kinugasa et al.

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