Oscillators – Automatic frequency stabilization using a phase or frequency... – Transistorized controls
Patent
1995-12-11
1997-03-11
Grimm, Siegfried H.
Oscillators
Automatic frequency stabilization using a phase or frequency...
Transistorized controls
331 11, 331 14, 331 36R, 331137, 331179, H03B 524, H03L 7099
Patent
active
056105606
DESCRIPTION:
BRIEF SUMMARY
The invention relates to an arrangement for generating a clock signal.
Digital video signal processing systems with features such as on-screen display of text and picture-in-picture for both television receiver and video tape recorder signal sources may require a clock signal that is phase locked to a horizontal synchronization signal, referred to as line-locked clock. It may be advantageous to form a phase-locked loop (PLL) system for line-locked clock generation for use as a building block in large scale CMOS video signal processing integrated circuits. In such PLL, it may be desirable to have, for example, a clock frequency that ranges from 25 MHz to 40 MHz with a jitter that is less than 2 nS. For such PLL it may be desirable to utilize only one pin for off-chip components. It may also be desirable to use the PLL system with each of the NTSC, PAL and SECAM systems.
It may further be advantageous to operate the PLL with input sync signal encountered in low-cost consumer video tape recorders without time-base correction where the horizontal sync can periodically make large phase changes such that the clock signal tracks such sync signal. It may be further desirable to rapidly reduce phase and frequency errors and minimize overshoot and jitter as the PLL settles into phase lock. In addition, it may be desirable to have the PLL discriminate between true output clock phase/frequency errors and those arising from contamination of the input horizontal sync signal with noise bursts or occasional missing pulses.
A PLL system, embodying an inventive feature, utilizes both digital and analog control of an R-C Voltage-Controlled Oscillator to acquire and maintain phase lock of an output clock with respect to an input horizontal sync signal. Depending on the magnitude and consistency of the output clock phase and frequency error, the system automatically selects one of, for example, five control modes of operation of varying sensitivity. The control modes of operation are such that large errors result in large, coarse corrective actions, and small errors result in small, or fine corrective actions.
In a PLL, embodying a different inventive feature, a frequency of an output signal of an oscillator is controlled in accordance with switched capacitors that are selectively coupled to a positive feedback path of the oscillator. A given group of switched capacitors selects a corresponding frequency range portion selected from an entire range of frequencies of the oscillator output signal. By varying the selection of the switched capacitors, the frequency range portion of the frequencies of the oscillator varies. Within the given frequency range portion, the frequency of the oscillator output signal is controllable by a control signal without varying the selection of the switched capacitors. The control signal can vary the oscillator frequency only within a limited portion of the entire range of frequencies. Therefore, stability and noise immunity is increased. Advantageously, jitter of the output signal of the oscillator is also reduced. Consequently, the oscillator can be realized with capacitors that can be fabricated within an integrated circuit. The integrated circuit may also include the remaining active circuit elements of the oscillator. When a large frequency error occurs between the horizontal synchronization signal and an output signal of the oscillator, the PLL operates in a coarse frequency correction mode.
In accordance with a further inventive feature, in each capacitor switching step that occurs in a sequential manner, a predetermined pair of the switched capacitors are either both coupled to the positive feedback path or both decoupled from the positive feedback path, in accordance with the direction of the frequency error. The frequency of the oscillator output signal changes progressively in the same direction, or monotoneously, in each switching step in the sequence of steps until the frequency error changes direction. When the frequency error changes direction, operation in the coarse frequency correc
REFERENCES:
patent: 4484152 (1984-11-01), Lee
patent: 4514705 (1985-04-01), Harzer
patent: 4516118 (1985-05-01), Wahlquist
patent: 4580107 (1986-04-01), Caldwell et al.
patent: 4594564 (1986-06-01), Yarborough, Jr.
patent: 4616259 (1986-10-01), Moran et al.
patent: 4654604 (1987-03-01), Smith et al.
patent: 4745372 (1988-05-01), Miwa
patent: 4797634 (1989-01-01), Filliman
patent: 4812783 (1989-03-01), Honjo et al.
patent: 4827225 (1989-05-01), Lee
patent: 4837781 (1989-06-01), Hickling
patent: 4843332 (1989-06-01), Cok et al.
patent: 4878231 (1989-10-01), Cok
patent: 4881048 (1989-11-01), Auneau et al.
patent: 4890071 (1989-12-01), Curtis
patent: 4918405 (1990-04-01), Herleikson
patent: 4920320 (1990-04-01), Matthews
patent: 4920322 (1990-04-01), Ruijs
patent: 4935706 (1990-06-01), Schenberg
patent: 4974081 (1990-11-01), Yokogawa
patent: 5053723 (1991-10-01), Schemmel
patent: 5157355 (1992-10-01), Shikakura et al.
patent: 5159292 (1992-10-01), Canfield et al.
patent: 5162910 (1992-11-01), Willis
patent: 5172076 (1992-12-01), Brown
patent: 5180995 (1993-01-01), Hayashi et al.
patent: 5191301 (1993-03-01), Mullgrav, Jr.
patent: 5239274 (1993-08-01), Chi
patent: 5298870 (1994-03-01), Cytera et al.
International Conference on EC-3-Energy Computer, Communication and Control Systems, vol. 3, 28 Aug. 1991, New Dehli, pp. 221-226, R. Pal et al "Frequency Tuning of Bipolar Ring Oscillators".
1991 IEEE International Solid-State Circuits Conference, vol. 34, 1 Feb. 1991, New York US, pp. 144-145, B. Lai et al, "A Monolithic 622MB/S Clock Extraction Data Retiming Circuit".
Telecommunications and Radio Engineering, vol. 40/41, No. 9, 1 Sep. 1986, Silver Springs US, pp. 105-109, V. Arutyunyan et al "Multichannel Generators of Shifted Square Pulses with RC Integrating Circuits".
Campbell, III Edward R.
Rodda William E.
Sauer Donald J.
Grimm Siegfried H.
Henig Sammy S.
Laks Joseph J.
RCA Thomson Licensing Corporation
Tripoli Joseph S.
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