Orientation optimization method of 2-pin logic cell

Details Orientation optimization method of 2-pin logic cell Orientation optimization method of 2-pin logic cell

2011-03-22

2011-03-22

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Optimization

C716S119000, C716S122000, C716S123000

Reexamination Certificate

active

07913219

ABSTRACT:
In an orientation optimization, at least one signal chain path starting from a signal source and passing through a series of M 2-pin logic cells is located according to a netlist. An output of the Nth 2-pin logic cell in the series of M 2-pin logic cells, where N<M, is set as a gravity point to attract an input of the (N+1)th 2-pin logic cell, thereby optionally flipping the (N+1)th 2-pin logic cell.

REFERENCES:
patent: 2007/0204252 (2007-08-01), Furnish et al.
Alupoaei et al.,“Net-Based Force-Directed Macrocell Placement for Wirelength Optimization”, Dec. 2002, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, No. 6, pp. 824-835.
Momenzadeh et al.,“Characterization, Test, and Logic Synthesis of And-Or-Invertor (AOI) Gate Design for QCA Implementation”, Dec. 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, No. 12, pp. 1881-1893.

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