Organization of dirty bits for a write-back cache

Details Organization of dirty bits for a write-back cache Organization of dirty bits for a write-back cache

2008-05-27

2008-05-27

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

11060141

ABSTRACT:
A cache system is constructed in accordance with an architecture that comprises a tag array into which tags are stored that are used to determine whether a hit or a miss into the cache system has occurred. Further, the cache system comprises a data array into which cache lines of data are stored, each cache line comprising a plurality of sub-lines, and each sub-line is adapted to be written back to a system memory separate from the other sub-lines. The cache system also comprises a controller coupled to the tag and data arrays. The tag array includes a cache-line dirty bit associated with each cache line and the data array includes a plurality of dirty bits for each cache line. The plurality of dirty bits comprises one sub-line dirty bit for each sub-line.

REFERENCES:
patent: 4742454 (1988-05-01), Robinson et al.
patent: 5155824 (1992-10-01), Edenfield et al.
patent: 5692150 (1997-11-01), Moriyama et al.
patent: 5692152 (1997-11-01), Cohen et al.
patent: 5778431 (1998-07-01), Rahman et al.
patent: 5784590 (1998-07-01), Cohen et al.
patent: 5802572 (1998-09-01), Patel et al.
patent: 5890217 (1999-03-01), Kabemoto et al.
patent: 5900011 (1999-05-01), Saulsbury et al.
patent: 6038674 (2000-03-01), Sasaki et al.
patent: 6128702 (2000-10-01), Saulsbury et al.
patent: 6205521 (2001-03-01), Schumann
patent: 6401173 (2002-06-01), Razdan et al.
patent: 6728838 (2004-04-01), Chauvel et al.
patent: 6785763 (2004-08-01), Garnett et al.
patent: 6848035 (2005-01-01), Akiyama et al.
patent: 2002/0078268 (2002-06-01), Lasserre
patent: 2004/0225829 (2004-11-01), Akiyama et al.
patent: 2006/0085600 (2006-04-01), Miyashita et al.
patent: 1 182 563 (2002-02-01), None
patent: 1 298 532 (2003-04-01), None
“Selective Write Back Cache Replacement Strategy”, IBM Technical Disclosure Bulletin, IBM Corp., New York, US, vol. 37, No. 6A, Jun. 1, 1994, pp. 199-200, XP000455742, ISN: 0018-8689.

Affiliated with

Also associated with

Rating

Organization of dirty bits for a write-back cache does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Organization of dirty bits for a write-back cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Organization of dirty bits for a write-back cache will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3939808