Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1979-02-09
1980-12-23
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Data refresh
361 49, 361189, 307238, G11C 1140
Patent
active
042414253
ABSTRACT:
An MOS dynamic random access memory (RAM) includes an array of memory cells arranged in rows and columns. The array is divided into two or more sub-arrays. In an operating cycle where a cell is being accessed for reading and/or writing, only the sub-array containing the accessed cell is fully selected while the other sub-arrays are partially selected. A fully selected sub-array is one in which both a row and a column are selected, whereas in a partially selected sub-array, only a row is selected. In the partially selected sub-array where only refreshing of the cells in the selected row takes place, the column decoders and drivers remain inactive throughout the memory cycle.
REFERENCES:
patent: 3737879 (1973-06-01), Greene
patent: 3811117 (1974-05-01), Anderson
patent: 3846765 (1974-11-01), DeVries
patent: 4106108 (1978-08-01), Cislaghi
Cenker Ronald P.
Clemons Donald G.
Huber, III William R.
Procyk Frank J.
Bell Telephone Laboratories Incorporated
Fears Terrell W.
Torsiglieri Arthur J.
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