Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-06-28
2004-11-02
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S779000, C257S786000, C361S808000, C174S256000
Reexamination Certificate
active
06812570
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit packages, and more particularly to an organic carrier member having low tin solders that is suitable for mounting a semiconductor device.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra-large scale integration technology creates significant challenges for the design and implementation of electrical connections between circuit components and external electrical circuitry.
Integrated circuit (IC) devices whether individual active devices, individual passive devices, multiple active devices within a single chip, or multiple passive and active dies within a single chip, require suitable input/output (I/O) connections between themselves and other circuit elements or structures. These devices are typically very small and fragile. Because of their size and fragility, they are commonly carried on substrates for support, i.e., carrier members.
Device miniaturization and the ever increasing density of semiconductor devices require an ever increasing number of I/O terminals, shorter connections and improvements in the electrical connections, heat dissipation and insulation characteristics of the carrier member. This problem is exacerbated in manufacturing semiconductor devices having a design rule of about 0.18 microns and under.
One technique that supports the increased device densities is the shift from peripheral wire bonding to area array chip interconnects. Area array chip interconnects use bumps or solder joints that directly couples the IC device, i.e., a semiconductor device, die or chip, to a carrier member. This technique accommodates an increased number of I/O terminals and provides electrical signals immediately below the chip, improving voltage noise margins and signal speed. One type of area array interconnect packaging technique is the flip chip (FC) solder interconnect on a carrier member.
In the flip chip assembly or package, the IC device and other devices are “bumped” with solder bumps or balls, i.e. a plurality of discrete solder bumps are formed over metal contacts on the surface of the chip. The chip is then turned upside down or “flipped” so that the device side or face of the IC device couples to the carrier member such as found in a ceramic or plastic carrier member having balls, pins or land grid arrays. The solder bumps of the device are then attached to the carrier member forming an electrical and mechanical connection.
As illustrated in
FIG. 1
, a conventional flip chip assembly
8
includes an IC semiconductor device or IC die
10
mechanically and electrically attached to substrate
16
by a plurality of solder bumps
12
connected to solder pads
14
on substrate
16
. Solder pads
14
are electrically connected to terminals
18
by internal wiring (not shown for illustrative convenience) throughout substrate
16
. Terminals
18
are then used to provide electrical connections to external circuitry. The assembly, thus, provides an electrical signal path from die
10
through solder/pad connections
12
/
14
through substrate
16
, by way of internal wiring, to an external connection by way of terminals
18
.
As shown, substrate
16
has a plurality of solder pads
14
, which are generally formed by screen printing a coating of solder on the substrate. Solder balls
12
on die
10
are generally formed by known solder bumping techniques and are conventionally formed of a high lead (Pb) solder, such as solders having from 97-95 wt. % Pb and from 3-5 wt. % of tin (Sn), which have a melting temperature of approximately 323° C. Substrate
16
can be made of ceramic or plastic materials. When the substrate is made of a ceramic, the electrical and mechanical interconnect between the die and substrate is conventionally achieved by reflowing the solder pads
14
and solder bumps
12
at a relatively high temperature, such as at 330° C. to 400° C., to join solder bumps
12
and pads
14
between the die and substrate
16
. It is preferable to have the high melting interconnection on the die, particularly dies having underfill, to avoid degradation of the die/substrate interconnection in subsequent thermal processing steps.
One problem associated with the flip chip packaging technique employing a plastic or organic substrate is that the interconnect processing temperature cannot be higher than the degradation temperature of the substrate, without adversely compromising the mechanical integrity of the substrate. To circumvent the need for high temperature to reflow the high lead solder bumps on the die, organic substrates are typically coated with eutectic solder (solders containing 63 wt. % Sn and 37 wt. % Pb) which melts at 183° C. When the high melting bumps
12
on die
10
are physically placed on eutectic solder pads on an organic substrate, reflowing the assembly at or above 183° C. melts the eutectic solder on the substrate which causes the molten eutectic to react with the solder bumps on the die to form a joint at a relatively lower temperature then the melting temperature of the high lead solder on the die.
Subsequent processing steps involve, for example, thermally attaching the die/substrate assembly to a circuit board. Thermal treatment during the regular manufacturing, however, may cause electrical discontinuity between the previously formed die and substrate interconnect. This leads to an interruption in the joint continuity and a gradual increase in the joint electrical resistance with time, particularly under high stress treatment. Even during the daily use of the package in a finished product, a large portion of heat energy generated during operation of the device is dissipated to the supporting substrate through the solder joints. The flow of heat energy through the joint establishes thermal gradients in the solder joints which lead to thermal migration of solder atoms in the interconnection, eventually resulting in discontinuity of the interconnection resulting in long-term filed reliability problems.
Accordingly, there is a continual need in semiconductor packaging technology for an improved solder interconnection that will resist thermal degradation and also exhibit long-term stability under normal operation and under high stress conditions.
SUMMARY OF THE INVENTION
An advantage of the present invention is an organic carrier member having solder alloys containing a low amount of tin that are suitable for mounting a semiconductor device.
Another advantage of the present invention is a device assembly that maintains reliable electrical connections under repeated heating and cooling cycles that occur during its normal operation.
Additional advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a carrier member for mounting a semiconductor device, such as an integrated circuit die, a capacitor, etc. The carrier member comprises: an organic substrate having a surface; a plurality of solder pads on the surface of the organic substrate that are suitable for receiving a device to be mounted thereto; and a plurality of electrical connections which are in electrical communication with the solder pads on the surface of the organic substrate.
Advantageously, the solder pads on the organic substrate comprise a low weight percent (wt. %) of tin (Sn). The solder pads preferably have a reflow temperature of less than about the decomposition temperature of the organic substrate. The organic substrate can comprise polyphenylene sulfide, polysulphone, polyethersulphone, polyarylsulphone, phenol, polyamide, bismaleimide-triazine, epoxy or mixtures thereof with optionally fiberous materials, such as glass fibers, to fabricate a lamin
Anderson Charles
Guardado Maria
Khan Mohammad Zubair
Master Raj N.
LandOfFree
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