Organic controlled collapse chip connector (C4) ball grid array

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

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257712, 257713, 257737, 257338, 257780, H01L 2348

Patent

active

059006757

ABSTRACT:
An integrated circuit chip package with an integrated chip carrier having differing coefficients of thermal expansion (CTE) in the x-y plane. The chip carrier is comprised of two main regions. The first is a core region having a CTE approximately equal to that of the semiconductor chip CTE. This core region also has approximately the same dimensions in the x-y plane as the semiconductor chip. The chip is mounted just above this core region. The second region is a peripheral region which surrounds the core region in the x-y plane. This second region has a CTE approximately equal to that of the printed circuit board CTE. During thermal cycling, the materials expand and contract. The core region expands at nearly the same rate as the chip and the area outside the chip footprint, the peripheral region, expands at a rate similar to that of the printed circuit board. This characteristic prevents thermal stress-induced fatigue on the package components and solder joints.

REFERENCES:
patent: 3290564 (1966-12-01), Wolff, Jr.
patent: 4654248 (1987-03-01), Mohammed
patent: 4893172 (1990-01-01), Matsumoto et al.
patent: 4914551 (1990-04-01), Anschel et al.
patent: 4942076 (1990-07-01), Panicker et al.
patent: 5086337 (1992-02-01), Noro et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5325265 (1994-06-01), Turlik et al.
patent: 5338967 (1994-08-01), Kosaki
patent: 5473119 (1995-12-01), Rosenmayer et al.
patent: 5481136 (1996-01-01), Kohmoto et al.
patent: 5493153 (1996-02-01), Arikawa et al.
patent: 5572070 (1996-11-01), Ross
patent: 5574630 (1996-11-01), Kresge et al.
patent: 5610442 (1997-03-01), Schneider et al.
patent: 5714803 (1998-02-01), Queyssac
patent: 5744863 (1998-04-01), Culnane et al.
patent: 5777386 (1998-07-01), Higashi et al.
patent: 5786635 (1998-07-01), Alcoe et al.
Mok, L.S., "Thermal Management of Silicon-based Multichip Modules", Thomas J. Watson Research IBM Research Division, Yorktown Heights, NY 10598.
Wilson, J.W., "A Low-Cost Metal Ball Grid Array for Flip Chip Die", IBM Microelectronics, Endicott, IEEE, 1995.
"Localized Control of Thermal Expansion in Electronic Assembly", IBM Technical Disclosure Bulletin, 39, No. 2, Feb. 1996.
Dietsch, H.E., et al., "Film on Metal Leaded Chip Carrier", IBM Technical Disclosure Bulletin, vol. Jun. 1988.
Dessauer, B., et al. "Copper-Clad Invar Heatsink", IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985.
Gazdik, C.E., et al., "Multilayer Polymer Substrate for Direct Chip Attachment", IBM Technical Bulletin, vol. 32, No. 3B, Aug. 1989.
C.N. Liu, "Matching the Thermal Coefficients of Expansion of Chips to Module Substrate," IBM Technical Disclosure Bulletin, vol. 19, No. 12, pp. 4666-4667 (May 1977).

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