Ordering rule and fairness implementation

Details Ordering rule and fairness implementation Ordering rule and fairness implementation

2005-09-29

2008-08-12

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S309000

Reexamination Certificate

active

07412555

ABSTRACT:
In one embodiment, a controller comprises one or more transaction queues, one or more age counter circuits, and a control circuit. The transaction queues are configured to store a plurality of transaction requests, each having a transaction type. The age counter circuits are configured to generate one or more age counters, where each age counter corresponds to a respective pair of transaction types. Coupled to receive an indication of an input transaction type corresponding to an input transaction request to the controller and coupled to the age counter circuits, the control circuit is configured to select at least one of the plurality of age counters to be stored with the input transaction request in the one or more transaction queues, each of the selected counters indicative of a relative age of the input transaction request with transaction requests of another transaction type.

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PCI Express, “PCI Express(TM) Base Specification,” Revision 1.0a, Apr. 15, 2003, pp. 90-97.

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