Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2007-07-27
2011-12-13
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S106000
Reexamination Certificate
active
08078791
ABSTRACT:
A device may generate a refresh signal that identifies a beginning of a refresh interval, determine the availability of banks of a memory device, and send refresh requests to the banks during the refresh interval based on the availability of the banks.
REFERENCES:
patent: 5265231 (1993-11-01), Nuwayser
patent: 5873114 (1999-02-01), Rahman et al.
patent: 5966725 (1999-10-01), Tabo
patent: 6115768 (2000-09-01), Yamamoto
patent: 6119199 (2000-09-01), Isobe
patent: 6226709 (2001-05-01), Goodwin et al.
patent: 6298413 (2001-10-01), Christenson
patent: 6360285 (2002-03-01), Fenwick et al.
patent: 6434082 (2002-08-01), Hovis et al.
patent: 6650586 (2003-11-01), Fanning
patent: 6871261 (2005-03-01), Proebsting
patent: 6920523 (2005-07-01), Le et al.
patent: 2002/0060940 (2002-05-01), Tomita
patent: 2002/0112117 (2002-08-01), Suh
patent: 2003/0081483 (2003-05-01), De Paor et al.
patent: 2003/0120861 (2003-06-01), Calle et al.
patent: 2005/0013185 (2005-01-01), Kim et al.
patent: 2007/0086261 (2007-04-01), Freebern
patent: 2007/0239930 (2007-10-01), Hearn
patent: 2010/0128547 (2010-05-01), Kagami
patent: WO 2007/013340 (2007-01-01), None
Toshiaki Kirihata, Paul Parries, David Hanson, Hoki Kim, John Golz, Gregory Fredeman, Raj Rajeevakumar, John Griesemer, Norman Robson, Alberto Cestero, Matt Wordeman, and Subramanian Iyer. “An 800MHz Embedded DRAM with a Concurrent Refresh Mode.” 2004. IEEE. ISSCC 2004.
American Heritage® Dictionary of the English Language. 2007. Houghton Mifflin. Definition of determine.
JEDEC. “DDR3 SDRAM Specification.” Apr. 2008. JEDEC. JESD79-3B. pp. 55-77 and 157-163.
Micron Technical Note, “Various Methods of DRAM Refresh”, Micron Technology Inc, TN-04-30, Feb. 1999, 4 pages.
T.H. Cormen et al., “Chapter 17, Greedy Algorithms”Introduction to Algorithms, MIT Electrical Engineering and Computer Science Series, Copyright date 1990, pp. 329-355, 35 pgs.
Keen John
Perla Srinivas
Venkatramani Anjan
Bragdon Reginald
Harrity & Harrity LLP
Juniper Networks, Inc.
Sadler Nathan
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