Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1997-09-16
2001-12-04
Niebling, John F. (Department: 2812)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S242000
Reexamination Certificate
active
06327636
ABSTRACT:
RELATED APPLICATIONS
The present application is related to a co-pending application entitled “PIPELINED READ TRANSFERS”, application Ser. No. 08/931,705, filed on even date herewith and assigned to the assignee of the present application.
FIELD OF THE INVENTION
The present invention relates generally to information processing systems and more particularly to an improved information transfer methodology in a computer related environment.
BACKGROUND OF THE INVENTION
As computer systems and networked computer systems proliferate, and become integrated into more and more information processing systems which are vital to businesses and industries, there is an increasing need for faster information processing and increased data handling capacity. Even with the relatively rapid state-of-the-art advances in processor technology, and the resulting increased processor speeds, a need still exists for faster processors and increased system speeds and more efficient information processing methodologies. This need is at least partially due to a growing number of computer applications and capabilities, including extensive network and rich graphics and display applications among others. As new applications for computers are implemented, new programs are developed and those programs are enriched with new capabilities almost on a daily basis. While such rapid development is highly desirable, there is a capability cost in terms of system speed.
One of the sources of inefficiency on the PCI bus in a typical computer environment is the manner in which “read” transactions are handled. When a master device in a computer system issues a read request to read data from a target device in the system, the master has no indication of when the target has gathered the data and has the requested data ready to be transferred back to the requesting master device. The manner in which the master becomes aware that the data is ready for transfer back to the master is to “poll” the target i.e. to re-attempt the request for access to the target. That methodology may result in many wasted attempts by the master before the data is ready to be returned. Each such attempt ties-up the bus and prevents other data transfers to take place during the attempt.
In addition, the target device has no definitive indication as to how much data is being requested to be read and returned to the master. The “READ”, “READ LINE” and “READ MULTIPLE” commands currently defined by the PCI specification (PCI Local Bus Specification, Production Version, Revision 2.1, Jun. 1, 1995) may give the target a general indication as to the amount of data being requested, but the target device may end up prefetching data beyond what the master actually needs. Although prefetching boosts performance in certain situations, it also wastes bus and memory bandwidth since only a small percentage of the data fetched may actually delivered to the master device.
Thus, there is a need for an improved information processing methodology and system in which information is more efficiently transferred between master and target devices during information processing transactions.
SUMMARY OF THE INVENTION
A method and apparatus is provided in which Pipelined Read Transfers (PRT) are implemented. The PRT methodology includes a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target a source address, a destination address and the transfer size for the data being requested. The PRT response phase involves the PRT request target becoming a PRT response master, i.e. a PCI bus master, and initiating a completion of the transaction that was requested in the originating PRT request. Pipelined read transfers are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlocks.
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Guthrie Guy Lynn
Kelley Richard Allen
Neal Danny Marvin
Thurber Steven Mark
International Business Machines - Corporation
McBurney Mark E.
Niebling John F.
Whitmore Stacey
Wilder Robert V.
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