Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
1999-09-27
2001-10-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S095000, C326S098000, C365S203000
Reexamination Certificate
active
06300801
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to an OR gate circuit, and more particularly to, a gate circuit, which can control the supply power by means of clocks, thus reducing the number of transistors and the layout area.
2. Description of the Prior Art
FIG. 1
shows a general OR gate circuit, the structure of which will be explained below.
First to third PMOS transistors P
1
to P
3
are connected between the supply terminal from which the supply power VCC is provided, and a node K
1
, to each gate thereof is inputted the input signals A, B and C. First to third NMOS transistors N
1
through N
3
are connected between the node K
1
and the ground terminal VSS, wherein each of the gates thereof is connected to the first through third PMOS transistors P
1
to P
3
. An inverter I is connected between the node K
1
and the output terminal OUT and inverts the potential of the node K
1
. The number of PMOS transistors P
1
through P
3
and the NMOS transistors N
1
through N
3
may be varied depending on the number of the input signals.
The operation of the OR gate circuit having the above-mentioned construction will be explained below.
If the input signals A, B and C are a low level, the PMOS transistors P
1
to P
3
are turned on and the NMOS transistors N
1
through N
3
are turned off. Thus, the potential of the node K
1
is maintained at a high level by the supply power VCC via the PMOS transistors P
1
through P
3
. At this time, the potential of the node K
1
, which is maintained at a high level, is inverted into a low level via the inverter I, so that the inverted potential can be outputted to the output terminal OUT.
If any one of the input signals A, B and C is a low level, for example the input signal B applied to the second PMOS transistor P
2
is a low level, the second PMOS transistor P
2
is turned on and the second NMOS transistor N
2
is turned off. However, as the input signals A and C applied to the gates of the first and third PMOS transistors P
1
and P
3
are maintained at a high level, the first and third PMOS transistors P
1
and P
3
is turned off, while the first and third NMOS transistors N
1
and N
3
is turned on. Therefore, the potential of the node K
1
becomes a low level. The potential of the node K
1
, which is maintained at a low level, is inverted into a high level via the inverter I, so that the inverted potential can be outputted to the output terminal OUT.
If all of the input signals A, B and C are HIGH, the first through third PMOS transistors P
1
through P
3
are turned off and the first through third NMOS transistors N
1
through N
3
are turned on. Therefore, the potential of the node K
1
becomes a LOW state. The potential of the node K
1
, which is maintained at LOW state, is inverted into HIGH state via the inverter I, so that the inverted potential can be outputted to the output terminal OUT.
As described above, since the conventional OR gate circuit is made of the pairs of the PMOS transistors and NMOS transistors, the number of the transistors becomes greater and thus increases the layout.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a OR gate circuit which can reduce the number of the transistors, thus reducing the layout area.
In order to accomplish the above object, the OR gate circuit according to the present invention is characterized in that it comprises a first switching means for supplying a supply power according to clock signals; a plurality of switching elements for outputting the supply power received via said first switching means to output means, respectively, in response to each of inverted input signals; and a second switching means for controlling said output terminals in response to said clock signals.
The state machine according to a first embodiment of the present invention is characterized in that it comprises a first delay means for delaying clock signals for a first set time; a second delay means for delaying output signals from said first delay means for a second set time; a circuit for logically combining said clock signals and said output signal from said second delay means; a first switching means for switching the supply of a supply power in response to the output from said circuit; a plurality of switching means each connected in parallel between said first switching means and an output terminal, said switching means being controlled depending on the input signals, respectively; a second switching means connected between said output terminal and a ground, said switching means being controlled depending on the output signals from the first delay means; and a latch means for latching the potential of said output terminal.
The state machine according to a second embodiment of the present invention is characterized in that it comprises a first delay means for delaying clock signals for a first set time; a second delay means for delaying output signals from said first delay means for a second set time; a circuit for logically combining said clock signals and said output signal from said second delay means; a first switching means for switching the supply of a supply power in response to the output from said circuit; a plurality of switching means each connected in parallel between said first switching means and a plurality of output terminals, said switching means being controlled depending on the input signals, respectively; a second switching means connected between said plurality of output terminal and a ground, said switching means being controlled depending on the output signals from the first delay means; a plurality of latch means each for latching each of the potentials of said plurality of output terminal depending on said clock clocks; and decoders for decoding the outputs from said plurality of latch means.
The state machine according to a third embodiment of the present invention includes a plurality of switching means connected between a supply power and an output terminal, said switching means being controlled input signals, respectively; transistors connected between said output terminal and a ground, the gate of which being connected to a supply power; and a latch circuit for latching the potential of said output terminal.
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Chang Daniel D.
Hyundai Electronics Industries Co,. Ltd.
Pennie & Edmonds LLP
Tokar Michael
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