Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2000-12-28
2002-02-26
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C438S027000, C438S129000, C438S125000, C438S116000
Reexamination Certificate
active
06350625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the provision of a plurality of diverse and novel optoelectronic packaging submount arrangements each of which incorporates a 90° C. electrical conductor turn. Moreover, the invention is further directed to the provision of novel methods of producing diverse optoelectronic packaging submount arrangements each incorporating 90° C. electrical conductor turns.
In order to conserve space in optoelectronic packaging it is generally desirable, and even frequently necessary, to position the optical fibers delivering the signals in a plane which is nearly coincident with the plane of the electronic board on which the transmitter, receiver, or transceiver module is based. A packaging problem which is perennially encountered in industry is presented by the fact that light must impinge against the face of receiver chips, while it is emitted from the face of VCSEL (vertical-cavity surface-emitting laser) chips which are employed as light emitters, so that when these optoelectronic chips are mounted on the electronic board, the light paths associated with the chips extend perpendicular to the axes of the optical fibers. This problem may be solved by either mounting the chips in the plane of the board and bending the optical path between the chips and the fibers by 90° C., or alternatively, by mounting the chips perpendicular to the plane of the board and bending or turning the electrical conductor paths between the chips and the board by 90° C.
2. Discussion of the Prior Art
In essence, the solution to the above-mentioned problems has been successfully pursued in the technology. However, the optical bend presents a challenging optical design problem, and the component which is utilized for the implementing of the bending process can be expensive and difficult to fabricate, as is described in M. S. Cohen et al. “Packaging Aspects of the Jitney Parallel Optical Interconnect”, Proc. 48
th
ECTC, pp. 1206-1215, 1998. In contrast with optical bending, the bending of an electrical conductor through an angle of 90 ° C. is relatively easily accomplished. For instance, a common implementation of such an electrical conductor bend of optoelectronic packaging involves the use of a flexible circuit, as described in P. Rosenberg, et al. “The PONI-1 Parallel-Optical Link”, Proc. 49
th
ECTC, pp. 763-769, 1999. However, such a flexible circuit implementation is costly and often is difficult to manipulate within very confined spaces. These frequently encountered problems are exacerbated as the data rates of the optoelectronic packaging increase, and consequently, the electrical paths are required decrease to in their lengths.
In order to solve this problem it has heretofore been proposed that electrical bending be used, but that each optoelectronic chip be mounted on a submount which incorporates electrical traces which provide a built-in 90° C. turn. The basic concept of a submount containing electrical traces with a built-in 90° C. turn, of course, is not new in the technology inasmuch as such submounts are commercially available, and for example, can be readily produced by depositing traces around a corner on a ceramic piece using thick-film screening technology.
SUMMARY OF THE INVENTION
Although basic principles in the production of optoelectronic packaging submount arrangements which incorporate 90° C. electrical conductor turns are generally known and employed in the technology, the present invention improves upon various important aspects thereof. In particular, pursuant to the invention, a number of advantages are derived thereby, as follows:
(a) A large number of submounts can be concurrently fabricated in parallel on a silicon wafer through the use of photolithography. This, in essence, will considerably reduce manufacturing expenditures so as to render it highly cost-effective.
(b) The dimensions of the traces being formed can be controlled precisely by the employment of the photolithography, in view of which they can be designed for high data-rate operation.
(c) The silicon material which is used for the submount facilitates a good degree of heat dissipation from the optoelectronic chip.
(d) The silicon material which is used for the submount, if desired, enables the fabrication of active devices on the submount.
(e) Finally, it is also possible to etch features into the submount which will aid in the packaging.
Accordingly, it is an object of the present invention to provide an optoelectronic packaging submount incorporating a 90° C. electrical conductor turn.
Another object of the present invention is to provide a plurality of optoelectronic packaging submounts having 90° C. electrical conductor turns as described herein, which may be concurrently and in parallel manufactured on a silicon wafer.
Yet another object of the present invention is to provide novel methods of producing optoelectronic packaging submounts having 90° C. electrical conductor turns in a highly economical and cost-effective manner.
REFERENCES:
patent: 5100808 (1992-03-01), Glenn
patent: 5249245 (1993-09-01), Lebby et al.
patent: 5804464 (1998-09-01), Beilstein, Jr. et al.
patent: 5907785 (1999-05-01), Palagonia
patent: 6207473 (2001-03-01), Hirai et al.
M.S. Cohen, et al.Packaging Aspects of the Jitney Parallel Optical Interconnect, consisting of 10 pages, No Date.
Paul Rosenberg, et al.The Poni-1 Parallel-Optical Link, Consisting of 6 pages, No Date.
Chey S. Jay
Cohen Mitchell S.
Cordes Steven A.
Hogan William K.
Ray Sudipta K.
International Business Machines - Corporation
Jones Josetta I.
Niebling John F.
Otterstedt, Esq. Paul J.
Scully Scott Murphy & Presser
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