Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-12-06
2009-08-11
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07574568
ABSTRACT:
A method, an apparatus and a system for a computing system implements a technique known as cache push that enhances a single writer invalidation protocol with the ability to optionally push data into another processor's cache without changing the memory consistency model being utilized by the method, apparatus and system.
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Cool Patent P.C.
Curtin Joseph P.
Intel Corporation
Peugh Brian R
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