Option fuse circuit using standard CMOS manufacturing process

Details Option fuse circuit using standard CMOS manufacturing process Option fuse circuit using standard CMOS manufacturing process

2002-12-25

2004-08-10

Le, Thong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S225700

Reexamination Certificate

active

06775189

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates to an option fuse circuit, and more particularly, to an option fuse circuit fabricated using standard CMOS manufacturing processes.
2. Description of the Prior Art
Within a variety of electronic products, memories (for example, ROM, DRAM, and SRAM, etc) have always been one of the most important components, as they perform a function of storing volatile and non-volatile data. A memory comprises a plurality of memory cells, each of which is used for storing one bit of digital data. The plurality of memory cells are usually lined up in an array, and manufactured in a form of an integrated circuit using semi-conductor manufacturing processes.
During ordinary semi-conductor manufacturing processes, because it is not possible for a yield of production of integrated circuits to reach 100%, a certain percentage of defective products is expected. Therefore, during the flow from manufacturing to shipping of ICs, a product-testing step is critical and not ignorable. Only through the process of product testing can malfunctioning or unusable products due to the yield issue in a semi-conductor manufacturing process be filtered out and eliminated, guaranteeing that customers are shipped well-functioning products. Through the above description one can see that product testing is extremely important in the semi-conductor manufacturing process.
Since there are a huge number of memory cells in a memory (usually from tens to hundreds of megabytes, for example, 64 Mb or 128 Mb, etc), the probability of a malfunction happening in at least one among these many memory cells is quite high. If there is one malfunctioning memory cell in a memory, the memory will be treated as a defected product and become unusable. This causes trouble for memory manufacturers. Therefore, in general, during designing a memory, beside a main memory cell array an additional set of redundant memory cells is appended, and dedicated circuitry is used for controlling and selecting connections between the set of redundant memory cells and the memory cell array. By utilizing this technique, when some memory cells at certain addresses of the memory cell array are found to malfunction during the product-testing step, the dedicated circuitry can be used for controlling the set of redundant memory cells to replace the function of those malfunctioning memory cells. As a result, it is not necessary to eliminate the memory just because of a small fraction of malfunctioning memory cells, and costs are reduced. The above-mentioned dedicated circuitry is usually called an option fuse circuit.
Please refer to FIG.
1
.
FIG. 1
shows a diagram of an option fuse circuit
10
according to the prior art. The option fuse circuit
10
comprises a PMOS transistor
12
, a PMOS transistor
14
, an NMOS transistor
16
, and an option fuse
18
. The transistors
14
,
16
are electrically connected to each other to form an inverter, wherein two gates are connected to each other to form an input node of the inverter, and two drains are connected to each other to form an output node of the inverter. A drain of the transistor
12
and one end of the option fuse
18
are electrically connected to the input node of the inverter, a gate of the transistor
12
is electrically connected to the output node of the inverter, and the output node of the inverter is pulled out as an output node Vout of the option fuse circuit
10
. Finally, sources of the transistors
12
,
14
are electrically connected to a system voltage Vdd, and a source of the transistor
16
and the other end of the option fuse
18
are electrically connected to ground Vss.
Please refer to FIG.
2
A and FIG.
2
B.
FIG. 2A
shows a layout diagram of the option fuse
18
in FIG.
1
. The option fuse
18
is usually laid out using a metal line segment or a poly line segment, and as shown in
FIG. 2B
, during the product-testing process the option fuse
18
can be cut by a laser according to testing results. Since the output node Vout of the option fuse circuit
10
shows different output signal values between situations of the option fuse
18
being cut and not being cut (Take the option fuse circuit
10
in
FIG. 1
for example, when the option fuse
18
is not cut, Vout shows a logical “1”, i.e. a high voltage. When the option fuse
18
is cut, Vout shows a logical “0”, i.e. a low voltage), output signal values of a plurality of the option fuse circuits
10
in the memory can be used to encode a combination of the redundant memory cells replacing the malfunctioned memory cells in the memory array.
However, in order to prevent the destruction of surrounding devices due to the laser cutting, it is usually necessary to preserve a sufficient space around the layout of the option fuse
18
(as shown in FIG.
2
A and
FIG. 2B
, an area of 5 &mgr;m×5 &mgr;m), and in order to proceed the laser cutting, an oxide layer on top of the option fuse
18
needs to be excavated to make an opening. However, the opening gives an entrance for contaminants, such as water vapor, to destroy surrounding devices, and this, as a result, lowers the reliability of these surrounding devices. This phenomenon is most significant when a number of the option fuse circuits
10
in the memory dramatically increases following a increasing memory storage space, because more option fuse circuits
10
means a larger number of openings, and hence greater opportunity of contamination of devices in the memory. On the other hand, laser cutting is relatively a much more time-consuming procedure since a large number of option fuses
18
need to be cut one after another during the product-testing process, and this causes a significantly long testing time.
In order to avoid the above-mentioned problems caused by using laser-cutting technology in an option fuse circuit, technologies according to the prior art also adopt flash memories in conjunction with proper circuit designs to realize the option fuse circuit. But since the manufacturing method of flash memories is not compatible with a standard CMOS manufacturing process, and has to include an additional polysilicon layer, the manufacturing costs are high.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide an option fuse circuit fabricated using standard CMOS manufacturing processes, so as to use only one polysilicon layer during the manufacturing process and not require laser cutting technology during testing, to solve the above-mentioned problems.
According to the claimed invention, an option fuse circuit manufactured with standard CMOS manufacturing processes comprises a latch comprising a first node and a second node, and being used for latching signals at the first and the second nodes; a comparator comprising two input nodes and an output node, wherein the two input nodes are electrically connected to the first and the second nodes respectively, the comparator being used for inputting the signals at the first and the second nodes respectively, and outputting a comparison signal by comparing the two signals; a first logic cell for storing a non-volatile data, comprising a first word line node and a first bit line node, wherein the first word line node is electrically connected to the output node of the comparator in order to input the comparison signal, the first bit line node being electrically connected to the first node; and a second logic cell for storing a non-volatile data, comprising a second word line node and a second bit line node, wherein the second word line node is electrically connected to the output node of the comparator in order to input the comparison signal, the second bit line node being electrically connected to the second node. The data stored in the first logic cell and the data stored in the second logic cell are complementary to each other.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment th

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