Optimum buffer placement for noise avoidance

Details Optimum buffer placement for noise avoidance Optimum buffer placement for noise avoidance

1998-06-12

2000-09-12

Teska, Kevin J.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 17, 703 13, G06F 1750

Patent

active

061171824

ABSTRACT:
A method for optimal insertion of buffers into an integrated circuit design. A model representative of a plurality of circuits is created where each circuit has a receiving node coupled to a conductor and a source. A receiving node is selected from the modeled plurality of circuits and circuit noise is calculated for the selected receiving node utilizing the circuit model. If the calculated circuit noise exceeds an acceptable value an optimum distance is computed from the receiving node on the conductor for buffer insertion. In a multi-sink circuit merging of the noise calculation for the two receiving circuits must be accomplished. If an intersection of conductors exists between the receiving node and the optimum distance a set of candidate buffer locations is generated. The method then prunes inferior solutions to provide an optimal insertion of buffers.

REFERENCES:
patent: 5019724 (1991-05-01), McClure
patent: 5402356 (1995-03-01), Schaefer et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5799170 (1998-08-01), Drumm et al.
patent: 5838581 (1998-11-01), Kuroda

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