Optimizing test code generation for verification environment

Details Optimizing test code generation for verification environment Optimizing test code generation for verification environment

2008-05-08

2010-11-30

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07844929

ABSTRACT:
A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.

REFERENCES:
patent: 7315973 (2008-01-01), Wise
patent: 7526742 (2009-04-01), Edwards
patent: 2001/0010091 (2001-07-01), Noy
patent: 2006/0229860 (2006-10-01), Azatchi et al.
patent: 2009/0018793 (2009-01-01), Sakarovitch et al.
patent: 2010/0088278 (2010-04-01), Wood et al.

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