Optimizing repeaters positioning along interconnects

Details Optimizing repeaters positioning along interconnects Optimizing repeaters positioning along interconnects

1999-09-02

2002-05-14

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06389581

ABSTRACT:

FIELD OF THE INVENTION
This application relates to integrated circuit (IC) design and, specifically, to interconnects propagation delay analysis in high speed, high density IC design.
BACKGROUND OF THE INVENTION
Forming interconnections in integrated circuit (IC), semiconductor fabrication in includes metallization. The purpose of metallization in semiconductor fabrication is to interconnect the various components of the IC. Metallization involves the deposition of a layer of conductive material, generally referred to as a metal layer, over the surface of the silicon substrate and the etching of a pattern in the metal layer to form the interconnections of the desired circuit. In automated IC design, the metal layer pattern is created by routing that implements the specified circuit. A typical IC includes more than one metal layer (e.g., M
1
, M
2
, . . . , and M
6
), the metal layers being individually created and then connections being made between the metal layers as needed.
As semiconductor design and fabrication improves, semiconductor technology scales become smaller. Semiconductor technology roadmaps predict, for example, that the number of metal (wiring) layers may reach 10 layers even in the 130 nm process generation, and the maximum clock frequencies will reach the gigahertz range even in the 180 nm process generation. It is further predicted that the interval between process generations may be somewhat less than three years.
With current and predicted technology scaling, the design for performance, manufacturability and reliability in high density, high performance deep-submicron ICs is increasingly dependent on IC interconnections design. In order to achieve high speed operations, special attention is paid to the method of interconnecting components in the IC. For instance, routing tools are increasingly required to combine considerations of signal, power/ground and clock distribution.
Interconnections in the IC form signal paths. For high speed signals, an interconnect and its environment becomes a relatively complex circuit element along which the signals propagate with finite speed. The complex circuit element has resistive, capacitive and inductive attributes that contribute to signal propagation time delays. With such attributes, the interconnect, also known in the context of ICs as a wire, net or line, is an important IC performance limiting factor. With interconnect delays dominating overall IC signal path delays, care is taken as to the characteristics of interconnects, their routing and the performance limiting factors that are associated with the interconnects.
For instance, a reflection of signal energy which is returned along an interconnect to the signal origin point may cause ringing or a “bumpy” rising edge. To maintain the integrity of signals propagating through interconnects, the geometry (e.g., length) of interconnects is controlled relative to the rise time of signals. Additionally, interconnects configured as transmission lines are typically terminated with a resistance corresponding to the characteristic impedance of such interconnects. However, further improvement in the design of interconnects is needed in order to achieve high speed operations in high density sub-micron ICs. The present invention addresses this and related problems.
SUMMARY OF THE INVENTION
A preferred embodiment of the present invention provides an aspect of interconnect design for optimizing delay characteristics of interconnects. The preferred embodiment further provides a method for analyzing the delay characteristics of interconnects for verifying interconnect design results. Interconnect delay characteristics are improved by inserting repeaters at predetermined intervals along interconnects in a metal layer. The metal layer is any one of a plurality of metal layers in a semiconductor device that embodies an integrated circuit (IC). Typically, each interconnect in the metal layer has at least one neighboring interconnect. The position of repeaters along every other interconnect in the metal layer is shifted relative to the position of repeaters along their neighboring interconnect(s). To achieve improved interconnect delay characteristics, the positioning of repeaters along interconnects is optimized by adjusting the position shift based on factors such as repeaters physical characteristics and signal waveforms.
In accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a method for optimizing repeaters positioning along interconnects. Specifically, the method includes inserting repeaters in positions along a first interconnect at predetermined intervals that are related to signal transition times. The method further includes inserting repeaters in positions along a second interconnect at the predetermined intervals, the second interconnect being a neighbor of the first interconnect. The positions along the second interconnect are offset, by a predetermined length, relative to the positions along the first interconnect so that the repeaters along the second interconnect are shifted relative to the repeaters along the first interconnect. The predetermined length is half (0.5) of the predetermined intervals such that repeaters are phase shifted by half, wherein the interconnect delay that corresponds to the offsetting by half of the predetermined interval minimizes the interconnect delay under worst case conditions. The repeaters are inserted to decrease interconnect delay and to make the interconnect delay scale linearly with an interconnect length.
In further accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a second method of analyzing interconnects tuning. The method of analyzing interconnects tuning also includes providing a metal layer in a semiconductor device, wherein the metal layer is patterned to have a plurality of interconnects, and inserting repeaters at predetermined intervals along each of the plurality of interconnects, the predetermined intervals being related to signal transition times. This analyzing method further includes providing a signal having a waveform to each of the plurality of interconnects, wherein each of the signal waveforms of signals that are provided to every other interconnect of the plurality of interconnects are offset, by a predetermined phase, relative to signal waveforms that are provided to interconnects neighboring the every other interconnect. With this setup, the delay characteristics of each interconnect are analyzed for selected values of the predetermined phase. One of the selected values of the predetermined phase correlates to half (0.5) of the predetermined interval.
In further accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a second method of analyzing interconnects tuning. The method of analyzing interconnects tuning also includes providing a metal layer in a semiconductor device, wherein the metal layer is patterned to have a plurality of interconnects, and inserting repeaters at predetermined intervals along each of the plurality of interconnects, the predetermined intervals being related to signals transition time. This analyzing method further includes providing a signal having a waveform to each of the plurality interconnects, wherein each of the signal waveforms of signals that are provided to every other interconnect of the plurality of interconnects are offset, by a predetermined phase, relative to signal waveforms that are provided to interconnects neighboring the every other interconnect. With this setup, the delay characteristics of each interconnect is analyzed for selected values of the predetermined phase. One of the selected values of the predetermined phase correlates to half (0.5) of the predetermined interval.
Advantages of the invention will be set forth, in part, in the description that follows and, in part, will be understood by those skilled in the art from the description herein. The advantages of the invention w

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