Optimizing long-path and short-path timing and accounting...

Details Optimizing long-path and short-path timing and accounting... Optimizing long-path and short-path timing and accounting...

2007-10-30

2007-10-30

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11002976

ABSTRACT:
Logic designs are optimized to satisfy long-path and short-path timing constraints for multiple process/operating condition corners. A path-based compilation phase determines an implementation for logic design paths, in part, by monitoring a set of paths that are important from a timing perspective and evaluating the timing performance of the set of monitored paths at one or more timing corners. A timing-analysis-based compilation phase determines transformations for converting sets of timing values from one timing corner to another timing corner. The compilation phase transforms timing delay values from one timing corner to another to facilitate analysis of timing performance at different corners. Timing slack values produced by analysis are transformed to map them from one timing corner to another. The transformed timing slack values from multiple corners are amalgamated. The amalgamated timing slack values are used by a compilation phase (that potentially only understands a single corner) to optimize a logic design for multiple corners.

REFERENCES:
patent: 6360356 (2002-03-01), Eng
patent: 6763506 (2004-07-01), Betz et al.
patent: 6973632 (2005-12-01), Brahme et al.

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