Optimizing locations of pins for blocks in a hierarchical...

Details Optimizing locations of pins for blocks in a hierarchical... Optimizing locations of pins for blocks in a hierarchical...

2006-09-26

2006-09-26

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07114142

ABSTRACT:
Method of optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design is provided and described. In one embodiment, a method of determining a plurality of locations of pins for each block of a physical design of a current integrated circuit includes retrieving physical design information from a prior physical design of a prior integrated circuit. The physical design information includes a routing congestion profile. Continuing, a router is provided a plurality of constraints based on the routing congestion profile. Then, the router is used to perform a top-level route for generating locations of pins for each block. Each pin of the block is created at a location where a global route enters the block or a location where a global route exits the block.

REFERENCES:
patent: 5604680 (1997-02-01), Bamji et al.
patent: 6230304 (2001-05-01), Groeneveld et al.
patent: 6243854 (2001-06-01), Lavin et al.
patent: 6275971 (2001-08-01), Levy et al.
patent: 6360356 (2002-03-01), Eng

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