Optimizing IC clock structures by minimizing clock uncertainty

Details Optimizing IC clock structures by minimizing clock uncertainty Optimizing IC clock structures by minimizing clock uncertainty

2006-08-22

2006-08-22

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C703S016000

Reexamination Certificate

active

07096442

ABSTRACT:
Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined characteristic along the first path. A second path from the launching cell toward the clock source is back-traced to a common one of the marked cells having the predetermined characteristic. Clock uncertainty is calculated based on the portion of the first path from the common marked cell having the predetermined characteristic to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.

REFERENCES:
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5258660 (1993-11-01), Nelson et al.
patent: 5298866 (1994-03-01), Kaplinsky
patent: 5414381 (1995-05-01), Nelson et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5467040 (1995-11-01), Nelson et al.
patent: 5475830 (1995-12-01), Chen et al.
patent: 5608645 (1997-03-01), Spyrou
patent: 5649167 (1997-07-01), Chen et al.
patent: 5715172 (1998-02-01), Tzeng
patent: 5835751 (1998-11-01), Chen et al.
patent: 5852640 (1998-12-01), Kliza et al.
patent: 5936867 (1999-08-01), Ashuri
patent: 6090150 (2000-07-01), Tawada
patent: 6205571 (2001-03-01), Camporese et al.
patent: 6219384 (2001-04-01), Kliza et al.
patent: 6266803 (2001-07-01), Scherer et al.
patent: 6305001 (2001-10-01), Graef
patent: 6311313 (2001-10-01), Camporese et al.
patent: 6324671 (2001-11-01), Ratzel et al.
patent: 6341363 (2002-01-01), Hasegawa
patent: 6487697 (2002-11-01), Lu et al.
patent: 6518788 (2003-02-01), Kasahara
patent: 6536022 (2003-03-01), Aingaran et al.
patent: 6550044 (2003-04-01), Pavisic et al.
patent: 6550045 (2003-04-01), Lu et al.
patent: 6564361 (2003-05-01), Zolotykh et al.
patent: 6578182 (2003-06-01), Kurokawa et al.
patent: 6606736 (2003-08-01), Kobayashi et al.
patent: 6618816 (2003-09-01), Ido et al.
patent: 6651224 (2003-11-01), Sano et al.
patent: 6665845 (2003-12-01), Aingaran et al.
patent: 6684373 (2004-01-01), Bodine et al.
patent: 6711724 (2004-03-01), Yoshikawa
patent: 6799308 (2004-09-01), You et al.
patent: 6810505 (2004-10-01), Tetelbaum
patent: 6836874 (2004-12-01), Batchelor et al.
patent: 6880141 (2005-04-01), Tetelbaum
patent: 6910194 (2005-06-01), Mielke et al.
patent: 6941532 (2005-09-01), Haritsa et al.
patent: 6954915 (2005-10-01), Batchelor
patent: 2002/0029361 (2002-03-01), Kasahara
patent: 2002/0073389 (2002-06-01), Elboim et al.
patent: 2002/0104035 (2002-08-01), Burns et al.
patent: 2002/0161947 (2002-10-01), Ikeda et al.
patent: 2003/0051222 (2003-03-01), Williams et al.
patent: 2003/0070151 (2003-04-01), Kurokawa et al.
patent: 2003/0074642 (2003-04-01), Haritsa et al.
patent: 2003/0074643 (2003-04-01), Schmitt et al.
patent: 2003/0115493 (2003-06-01), Wong et al.
patent: 2003/0121013 (2003-06-01), Moon et al.
patent: 2003/0149943 (2003-08-01), Yoshikawa
patent: 2003/0159118 (2003-08-01), Lindkvist
patent: 2003/0177464 (2003-09-01), Takechi et al.
patent: 2003/0212971 (2003-11-01), Rodgers et al.
patent: 2004/0003360 (2004-01-01), Batchelor et al.
patent: 2004/0015801 (2004-01-01), Mielke et al.
patent: 2004/0025129 (2004-02-01), Batchelor
patent: 2004/0107408 (2004-06-01), Sano et al.
patent: 2004/0123259 (2004-06-01), You et al.
patent: 2004/0268279 (2004-12-01), Oleksinski et al.
patent: 2005/0000108 (2005-01-01), Lu et al.
patent: 2005/0132313 (2005-06-01), Lindkvist
patent: 09218888 (1997-08-01), None
NA9402189, “Process-Variation-Tolerant Zero Skew Clock Routing”, IBM Technical Disclosure Bulletin, vol. 37, No. 2A, Feb. 1994, pp. 189-198 (10 pages).
Feehrer, “The Effect of Propagation Delay Uncertainty on the Speed of Time-of-Flight Digital Optoelectronic Circuits”, Journal of Lightwave Technology, vol. 14, No. 12, pp. 2698-2713, Dec. 1996.
Pullela et al., “Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 2, pp. 210-215, Feb. 1997.
Balatsos et al., “Low-Skew Clock Generator with Dynamic Impedance and Delay Matching”, IEEE International Solid-State Circuits Conference, Feb. 15, 1999, pp. 182-183.
Feehrer, “The Effect of Propagation Delay Uncertainty on the Speed of Time-of-Flight Digital Optoelectronic Circuits”, Journal of Lightwave Technology, vol. 14, No. 12, Dec. 1996, pp. 2698-2713.
Lee, “A Multilevel Parasitic Interconnect Capacitance Modeling and Extraction for Reliable VLSI On-Chip Clock Delay Evaluation”, IEEE Journal of Solid-State Circuits, vol. 33, No. 4, Apr. 1998, pp. 657-661.

Affiliated with

Also associated with

Rating

Optimizing IC clock structures by minimizing clock uncertainty does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Optimizing IC clock structures by minimizing clock uncertainty, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimizing IC clock structures by minimizing clock uncertainty will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3617937