Optimizing hardware TLB reload performance in a...

Details Optimizing hardware TLB reload performance in a... Optimizing hardware TLB reload performance in a...

2004-06-30

2009-06-02

Sough, Hyung S (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

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C711S150000, C711S151000, C711S158000, C711S202000, C711S203000, C711S205000, C711S206000, C711S216000

Reexamination Certificate

active

07543132

ABSTRACT:
A method and apparatus for improved performance for reloading translation look-aside buffers in multithreading, multi-core processors. TSB prediction is accomplished by hashing a plurality of data parameters and generating an index that is provided as an input to a predictor array to predict the TSB page size. In one embodiment of the invention, the predictor array comprises two-bit saturating up-down counters that are used to enhance the accuracy of the TSB prediction. The saturating up-down counters are configured to avoid making rapid changes in the TSB prediction upon detection of an error. Multiple misses occur before the prediction output is changed. The page size specified by the predictor index is searched first. Using the technique described herein, errors are minimized because the counter leads to the correct result at least half the time.

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