Optimizing exit latency from an active power management state

Details Optimizing exit latency from an active power management state Optimizing exit latency from an active power management state

2007-02-13

2007-02-13

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C713S320000, C713S323000, C713S324000, C379S323000, C379S395010, C455S127100, C455S522000, C455S572000, C455S574000

Reexamination Certificate

active

10749619

ABSTRACT:
A transmitting device and a receiving device are coupled together via an interconnect. An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline. At the time the electrical idle ordered set has been recognized at the end of the receiver logic pipeline, the power management unit checks for activity on the interconnect. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be turned off.

REFERENCES:
patent: 5652895 (1997-07-01), Poisner
patent: 5721935 (1998-02-01), DeSchepper et al.
patent: 5890004 (1999-03-01), Poisner
patent: 5991635 (1999-11-01), Dent et al.
patent: 6021506 (2000-02-01), Cho
patent: 6131167 (2000-10-01), Cruz
patent: 6272644 (2001-08-01), Urade et al.
patent: 6282665 (2001-08-01), Cruz
patent: 6463542 (2002-10-01), Yu et al.
patent: 2003/0185308 (2003-10-01), Schoenborn
patent: 2004/0103333 (2004-05-01), Martwick et al.
patent: 2005/0097378 (2005-05-01), Hwang
patent: 2005/0149768 (2005-07-01), Kwa et al.
patent: PCT/US2004/043418 (2004-12-01), None
International application No. PCT/US2004/043418, International Preliminary Report on Patentability.

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