Optimizing dynamic power characteristics of an integrated...

Details Optimizing dynamic power characteristics of an integrated... Optimizing dynamic power characteristics of an integrated...

2007-06-26

2007-06-26

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

10927919

ABSTRACT:
The present invention optimizes the dynamic power characteristics of an integrated circuit (IC) chip. The IC chip includes a plurality of layers, wherein at least one of the layers is a power mesh layer that provides power to the IC chip, and includes a ground (Vss) net. The method includes providing at least one dummy metal mesh layer, and coupling the dummy metal mesh layer to the Vss net on the power mesh layer thereby increasing the capacitance on the Vss net.

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