Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-12-21
2004-09-07
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
06789163
ABSTRACT:
FIELD OF THE INVENTION
The claimed invention relates generally to the field of disc drive data storage devices, and more particularly, but not by way of limitation, to an apparatus and method for optimizing the transfer of data between a host device and a disc drive using an access command sort strategy that involves partial purging of write commands based on the amount of write data pending in a buffer.
BACKGROUND
A disc drive is a data storage device used to store digital data. A typical disc drive includes a number of rotatable magnetic recording discs that are axially aligned and mounted to a spindle motor for rotation at a high constant velocity. A corresponding array of read/write heads access fixed sized data blocks (sectors) on tracks of the discs to write data to and to read data from the discs.
Disc drives are provided with servo control circuitry to move the heads to the various tracks, read/write channel circuitry to write data to and read data from the discs, and interface control circuitry to facilitate communication and data transfer with a host device. A disc drive is typically configured to operate in accordance with an industry standard interface protocol, such as Small Computer Systems Interface (SCSI). Communications and data transfers are carried out between host and drive in accordance with this protocol.
Disc drives of the present generation typically accommodate command queuing, which allows multiple input/output (I/O) commands to be received in a command queue and executed by the drive in an order different than that received. SCSI protocols currently support up to 256 pending commands in the command queue. A search strategy is used to execute the commands in an order that will provide the highest transfer rate. For example, if several commands require access to data blocks close to the current position of the heads, and other commands require access to data blocks at distant locations on the discs, the drive may proceed to execute all of the local accesses before moving the heads to the distant locations and accessing the data blocks at the distant locations to minimize seek time (i.e., time spent moving from one track to the next).
The time required for a particular data block to rotate around and reach the head (latency) is an important factor when selecting the execution order, as delays in waiting for the disc to rotate significantly decrease the resulting transfer rate. Selection of the execution order typically includes estimating how much time it would take to reach each of the data blocks associated with the pending access commands based on latency and the time required to perform any necessary head switches and seeks.
A disc drive can typically employ various run-time selectable strategies (parameters) to improve data transfer performance, such read on arrival (ROA) and read look ahead (RLA). ROA and RLA generally entail reading data blocks and placing the contents into the data buffer even though the host has not specifically requested the data from such data blocks, on the basis that the host may request the data in the near future.
ROA involves performing a seek command to move the head to a destination track on which a target data block resides, and commencing to read the preceding data blocks on the track until the target data block reaches the head. By contrast, RLA involves receiving a command to move to a new target track, but because the target data block is a large angular distance away from the head, the drive delays seeking to the new track and instead maintains the head on the current track and reads additional data blocks on the current track before moving to the destination track and reading the target data block. The foregoing strategies can provide improved performance under certain circumstances, such as when the command stream has a high degree of locality.
Another run-time selectable parameter that can improve data transfer performance is write caching. Write caching involves delaying the writing of data received from the host in favor of execution of other previously requested accesses (as opposed to immediately writing the data upon receipt). Advantages associated with write caching include the fact that more commands are available to choose from during the sorting strategy, which statistically improves overall access times. Having more write commands pending in the command queue improves the possibility of combining multiple adjacent write commands into a single, larger write operation, thereby reducing the total number of physical disc accesses required to write the data. Another advantage of write caching is that a command complete status is immediately conveyed to the host device upon the loading of the write data into the buffer.
However, allowing write data to linger in the buffer presents some disadvantages as well. Besides the risk of loss of data in the event of a power outage or other anomalous condition, the presence of large amounts of accumulated write data in the buffer takes up valuable space that could be utilized for readback data. Also, controller firmware routines typically only allow a maximum aging of any pending write command; thus, a substantial drop in observed data transfer rate may occur if the interface circuit is forced to service a large number of write commands to purge old write data to the discs.
Accordingly, there is a need for improvements in the art to provide effective control of cached write data in a disc drive to maximize data transfer performance, stabilize and minimize write command response time, and reduce the penalty encountered through the addition of new access commands to the command queue. It is to such improvements that the present invention is directed.
SUMMARY OF THE INVENTION
In accordance with preferred embodiments, a disc drive data storage device is provided which includes at least one data transducing head adjacent a data recording surface of a rotatable disc. Data are stored on the data recording surface in a number of blocks (“sectors”). A hardware and/or firmware based interface circuit includes a data buffer to temporarily store data being transferred between the data recording surface and the host device. A control processor operates in conjunction with the interface circuit to direct the transfer of data.
The interface circuit receives access commands from the host device including read commands identifying read data to be retrieved from the disc drive data storage device and write commands identifying write data to be stored by the data storage device. Write caching is activated so that the write data are temporarily stored in the buffer pending subsequent execution of the associated write commands.
A phase time is identified for each pending access command as an elapsed time to configure the data storage device to initiate servicing of the access command. The access commands are executed in an order selected in relation to the identified phase times, with an emphasis on executing the pending access command having the shortest phase time. This is referred to herein as mode 1 operation.
The interface circuit continuously monitors the total amount of write data that accumulates in the buffer. When the total amount of accumulated write data reaches a first selected threshold, the interface circuit transitions to what is referred to as mode 2 operation.
During mode 2, an intermediary phase interval between the completion of each write command and the start of each remaining write command is determined to identify a thread of write commands having an associated intermediary phase interval less than a predetermined phase interval level. If such a thread is located, the interface circuit proceeds to execute the write commands in the thread. This occurs even if another read or write command potentially has a smaller phase time than the first write command in the thread. If multiple threads are identified, the interface circuit will either execute a subset of the threads (leaving some threads for future execution at a later time), or will proceed to execute all of th
Fox Travis D.
Olds Edwin Scott
Ellis Kevin L.
Fellers , Snider, et al.
Seagate Technology LLC
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