Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-02-07
2010-02-23
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S154000, C710S056000
Reexamination Certificate
active
07669028
ABSTRACT:
Embodiments of the present invention optimize data bandwidth across an asynchronous buffer in a system with a variable clock domain. A move signal may be asserted to transfer data associated with a command into the asynchronous buffer. After the data has been moved into the buffer, an acknowledge signal may indicate that the transfer is complete. A launch signal may transfer the data in the asynchronous buffer to memory. Embodiments of the present invention allow the processing of a next command to begin at the earliest possible time while data associated with a previous command is being transferred into and out of the buffer, thereby increasing throughput and improving performance.
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Bellows Mark D.
McKevett Brian M.
Ozguner Tolga
International Business Machines - Corporation
Patterson & Sheridan LLP
Peugh Brian R
Thammavong Prasith
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