Optimizing compiler having data cache prefetch spreading

Details Optimizing compiler having data cache prefetch spreading Optimizing compiler having data cache prefetch spreading

1996-08-23

1998-12-29

Trammell, James P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395705, 395383, 395584, 395588, 711118, 711137, 711213, 711217, 711171, G06F 945, G06F 1208

Patent

active

058549340

ABSTRACT:
A method of scheduling prefetch instructions in a compiler is described that improves performance by minimizing the performance degradation due to dirty cache misses. The method determines the length N of a loop (step 66). The number of prefetch instructions were M within that loop are then determined (step 68). A prefetch spacing P is then calculated according to the formula P=N/M, where the length of the loop is expressed in cycles (step 70). This prefetch spacing is then attached to each prefetch instruction and the instruction scheduler schedules the prefetch instructions so as to space the prefetch instructions apart by approximately the prefetch spacing P (step 72). After the scheduler arranged for P cycles, a prefetch instruction will be assigned a higher priority for scheduling in the next lot.

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Chi et al., "Compiler driven data cache prefetching for high performance computers," Proceedings of TENCON'94--IEEE Region 10's 9th Annual Int'l Conf. on: `Frontiers of Computer Technology`, Singapore, Aug. 1994.
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Blainey, R. J., "Instruction Scheduling in the TOBEY compiler," IBM J. Res. Develop, vol. 38, No. 5, Sep. 1994, pp. 577-593.
Farkas, Keith I. and Jouppi, Norman P., Complexity/Performance Tradeoffs with Non-Blocking Loads, IEEE, 1994, pp. 211-222.
Mowry, Todd; Lam, Monica and Gupta,Anoop, "Design and Evaluation of a Compiler Algorithm for Prefetching," Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 1992.

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