Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-15
2010-06-15
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07739630
ABSTRACT:
Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.
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Mitch Heins, Pyxis Technology, EE Times Online, In the Eye of the DFM/DFY Storm, May 25, 2007, http://www.eetimes.com/showArticle.jhtml;jsessionid=5L54GMGMWMJKOQSNDLOSKHSCJUNN2JVN?articleID=199702741.
Wilbur Luo, EE Times Online, A Balanced Approach to Chip Optimization, Apr. 24, 2006, http://www.eetimes.com/showArticle.jhtml;jsessionid=5L54GMGMWMJKOQSNDLOSKHSCJUNN2JVN?articleID=185303804.
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Jason Cong et al., Advanced Routing Techniques for Nanometer IC Designs, ICCAD 2006 Routing Tutorial.
Chen Hsi-Chuan
Cheng Chih-Liang
Li Jeong-Tyng
Yang Chung-Do
Do Thuan
SpringSoft USA, Inc.
Van Pelt & Yi & James LLP
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