Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1999-04-22
2000-09-19
Powell, William
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
216 38, 216 88, 438713, 438734, 438745, H01L 2100
Patent
active
061211494
ABSTRACT:
The reliability of in-laid metallization patterns, e.g., of copper or a copper-based alloy is significantly enhanced by voidlessly filling recesses formed in the dielectric layer surface by an electroplating process. Embodiments of the present invention include preventing "pinching-off" of the recess opening due to formation of overhanging nucleation/seed layer deposits at the corners of the opening as a result of locally increased rates of deposition. Embodiments of the present invention also include providing a dual-layered dielectric layer comprising dielectric materials having different lateral etching rates when subjected to a preselected etching process, for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, which tapered width profile effectively prevents formation of overhanging deposits, which overhanging deposits can result in occlusion and void formation during electroplating to fill the recesses.
REFERENCES:
patent: 4543707 (1985-10-01), Ito et al.
Avanzino Steven C.
Lukanc Todd P.
Wang Fei
Advanced Micro Devices , Inc.
Powell William
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