Optimized trench/via profile for damascene filling

Details Optimized trench/via profile for damascene filling Optimized trench/via profile for damascene filling

1999-04-22

2000-09-12

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

216 38, 216 88, 438713, 438734, 438745, H01L 2100

Patent

active

061177822

ABSTRACT:
In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improved reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing "pinching-off" of the recess opening due overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Embodiments also include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper (sacrificial) lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer. The tapered width profile of the recess effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during electroplating for filling the recesses. After electroplating, the recess-filled, plated surface is subjected to planarization processing, as by CMP, wherein the entire thickness of the second, upper lamina of the dielectric layer is removed.

REFERENCES:
patent: 4372034 (1983-02-01), Bohr

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