Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-28
2006-03-28
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07020864
ABSTRACT:
Technology mapping techniques are provided for converting a user design for a programmable integrated circuit to a network of programmable logic blocks. The technology mapping process attempts to combine each non-strategic node and predecessor nodes in one programmable logic block according to only one type of node merging group. If the non-strategic node can be feasibly merged with predecessor nodes according to the merging group, they are grouped into a programmable logic block. The technology mapping process tries to merge strategic nodes with various merging groups of predecessor nodes to form a programmable logic block. The technology mapping process can select the best merging group for the strategic node by using a cost metric. The cost metric can consist of depth and area information of a network for the logic cone.
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Altera Corporation
Kik Phallaka
Smith Matthew
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