Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1995-12-26
1999-01-19
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438633, 438697, 438926, H01L 21461, H01L 2144
Patent
active
058613420
ABSTRACT:
A method of improving the planarity of spin-on-glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces in a trace layer that exceed a predetermined distance are provided with dummy lines having a specific geometry in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined distance is greater than approximately 1 micrometer, as for example in the range of approximately 3 to 6 micrometers. In some applications, both the active conductive traces and the dummy lines are formed from a metallic material that is deposited in one single step with a passivation layer being deposited over both the conductive traces and the raised lines prior to application of the spin-on glass layer.
REFERENCES:
patent: 4775550 (1988-10-01), Chu et al.
patent: 4916514 (1990-04-01), Nowak
patent: 5003062 (1991-03-01), Yen
patent: 5089442 (1992-02-01), Olmer
patent: 5173448 (1992-12-01), Yanagi
patent: 5182235 (1993-01-01), Eguchi
patent: 5278105 (1994-01-01), Eden et al.
patent: 5441915 (1995-08-01), Lee
patent: 5461010 (1995-10-01), Chen et al.
patent: 5470802 (1995-11-01), Gnade et al.
patent: 5476817 (1995-12-01), Numata
patent: 5488015 (1996-01-01), Havemann et al.
patent: 5494853 (1996-02-01), Lur
patent: 5494854 (1996-02-01), Jain
patent: 5510293 (1996-04-01), Numata
patent: 5618757 (1997-04-01), Bothra et al.
patent: 5639697 (1997-06-01), Weling et al.
Ichikawa, et al., "Multilevel Interconnect System for 0.35um CMOS Lsi's with Metal Dummy Planarization Process and Thin Tungsten Wirings", Jun. 27-29, 1995 VMIC Conference, 1995 ISMIC--104/95/0254.
Gabriel Calvin T.
Weling Milind G.
Everhart Caridad
VLSI Technology Inc.
LandOfFree
Optimized structures for dummy fill mask design does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Optimized structures for dummy fill mask design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Optimized structures for dummy fill mask design will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1246419